PLLs & Clock Networks
Figure 2–43. Global & Regional Clock Connections from Top & Bottom Clock Pins & Enhanced PLL Outputs
Notes (1), (2), and (3)
CLK15
CLK14
CLK13
CLK12
PLL5_FB
PLL11_FB
PLL 11
PLL 5
c0 c1 c2 c3 c4 c5 c0 c1 c2 c3 c4 c5
PLL5_OUT[2..0]p
PLL5_OUT[2..0]n
PLL11_OUT[2..0]p
PLL11_OUT[2..0]n
RCLK31
RCLK30
RCLK29
RCLK28
RCLK27
Regional
Clocks
RCLK26
RCLK25
RCLK24
G15
G14
G13
G12
Global
Clocks
G4
G5
G6
G7
RCLK8
RCLK9
RCLK10
RCLK11
Regional
Clocks
RCLK12
RCLK13
RCLK14
RCLK15
PLL12_OUT[2..0]p
PLL12_OUT[2..0]n
PLL6_OUT[2..0]p
PLL6_OUT[2..0]n
c0 c1 c2 c3 c4 c5 c0 c1 c2 c3 c4 c5
PLL 12
PLL 6
PLL12_FB
PLL6_FB
CLK4
CLK6
CLK5
CLK7
Notes to Figure 2–43:
(1) EP2S15 and EP2S30 devices only have two enhanced PLLs (5 and 6), but the connectivity from these two PLLs to
the global and regional clock networks remains the same as shown.
(2) If the design uses the feedback input, you lose one (or two, if FBIN is differential) external clock output pin.
(3) The enhanced PLLs can also be driven through the global or regional clock netowrks. The global or regional clock
input can be driven by an output from another PLL, a pin-driven dedicated global or regional clock, or through a
clock control block provided the clock control block is fed by an output from another PLL or a pin-driven dedicated
global or regional clock. An internally generated global signal cannot drive the PLL.
2–64
Altera Corporation
May 2007
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
