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CLK14_6N 参数 Datasheet PDF下载

CLK14_6N图片预览
型号: CLK14_6N
PDF下载: 下载PDF文件 查看货源
内容描述: 的Cyclone III器件手册 [Cyclone III Device Handbook]
分类和应用:
文件页数/大小: 274 页 / 7302 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family  
5–25  
PLL Cascading  
Figure 5–19 shows using GCLK while cascading PLLs.  
Figure 5–19. PLL Cascading Using GCLK  
Five Clock  
Control Blocks  
Output from PLL  
Input to PLL  
CLK[8..11]  
4
2
PLL  
3
PLL  
2
2
5
1
20 GCLK[10..14]  
GCLK[0:19]  
Output from PLL  
Remote clock  
from two Clock  
pins at adjacent  
5
2
2
edge of device  
1
Five Clock  
Control Blocks  
20  
GCLK[0:19]  
4
GCLK[0..4]  
CLK[0..3]  
CLK[4..7]  
GCLK[5..9]  
GCLK[0:19]  
20  
Five Clock  
Control Blocks  
1
2
2
5
GCLK[0:19]  
20  
Output from PLL  
GCLK[15..19]  
1
PLL  
1
PLL  
4
5
2
2
CLK[12..15]  
Five Clock  
Control Blocks  
Output from PLL  
Consider the following guidelines when cascading PLLs:  
Set the primary PLL to low bandwidth to help filter jitter. Set the secondary PLL to  
high bandwidth to be able to track the jitter from the primary PLL. You can view  
the Quartus II software compilation report file to ensure the PLL bandwidth  
ranges do not overlap. If the bandwidth ranges overlap, jitter peaking can occur in  
the cascaded PLL scheme.  
1
You can get an estimate of the PLL deterministic jitter and static phase error  
(SPE) by using the TimeQuest Timing Analyzer in the Quartus II software.  
Use the SDC command "derive_clock_uncertainty" to direct TimeQuest to  
generate a report titled "PLLJ_PLLSPE_INFO.txt" in your project directory.  
Then, use "set_clock_uncertainty" commands to add jitter and SPE values to  
your clock constraints.  
July 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 1  
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