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CLK14_6N 参数 Datasheet PDF下载

CLK14_6N图片预览
型号: CLK14_6N
PDF下载: 下载PDF文件 查看货源
内容描述: 的Cyclone III器件手册 [Cyclone III Device Handbook]
分类和应用:
文件页数/大小: 274 页 / 7302 K
品牌: ALTERA [ ALTERA CORPORATION ]
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5–28  
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family  
PLL Reconfiguration  
Figure 5–21 shows a functional simulation of the PLL reconfiguration feature.  
Figure 5–21. PLL Reconfiguration Scan Chain  
scandata  
Dn  
D0  
LSB  
scanclk  
scanclkena  
scandataout  
Dn_old  
D0_old  
Dn  
configupdate  
scandone  
areset  
1
When reconfiguring the counter clock frequency, the corresponding counter phase  
shift settings cannot be reconfigured using the same interface. You can reconfigure  
phase shifts in real time using the dynamic phase shift reconfiguration interface. If  
you reconfigure the counter frequency, but wish to keep the same non-zero phase shift  
setting (for example, 90°) on the clock output, you must reconfigure the phase shift  
after reconfiguring the counter clock frequency.  
Post-Scale Counters (C0 to C4)  
You can configure multiply or divide values and duty cycle of post-scale counters in  
real time. Each counter has an 8-bit high time setting and an 8-bit low time setting.  
The duty cycle is the ratio of output high or low time to the total cycle time, which is  
the sum of the two. Additionally, these counters have two control bits, rbypass, for  
bypassing the counter, and rselodd, to select the output clock duty cycle.  
When the rbypassbit is set to 1, it bypasses the counter, resulting in a divide by one.  
When this bit is set to 0, the PLL computes the effective division of the VCO output  
frequency based on the high and low time counters. For example, if the post-scale  
divide factor is 10, the high and low count values is set to 5 and 5 respectively, to  
achieve a 50–50% duty cycle. The PLL implements this duty cycle by transitioning the  
output clock from high-to-low on the rising edge of the VCO output clock. However, a  
4 and 6 setting for the high and low count values, respectively, would produce an  
output clock with 40–60% duty cycle.  
The rseloddbit indicates an odd divide factor for the VCO output frequency with a  
50% duty cycle. For example, if the post-scale divide factor is three, the high and low  
time count values are 2 and 1, respectively, to achieve this division. This implies a  
67%–33% duty cycle. If you need a 50%–50% duty cycle, you must set the rselodd  
control bit to 1 to achieve this duty cycle despite an odd division factor. The PLL  
implements this duty cycle by transitioning the output clock from high-to-low on a  
falling edge of the VCO output clock. When you set rselodd= 1, subtract 0.5 cycles  
from the high time and add 0.5 cycles to the low time.  
For example:  
Cyclone III Device Handbook  
Volume 1  
July 2012 Altera Corporation  
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