4–4
Chapter 4: Embedded Multipliers in the Cyclone III Device Family
Architecture
Figure 4–2 shows the multiplier block architecture.
Figure 4–2. Multiplier Block Architecture
signa
signb
aclr
clock
ena
D
Q
Q
Data A
Data B
ENA
Data Out
D
Q
CLRN
ENA
CLRN
D
ENA
Output
Register
Input
Register
CLRN
Embedded Multiplier Block
Input Registers
You can send each multiplier input signal into an input register or directly into the
multiplier in 9- or 18-bit sections, depending on the operational mode of the
multiplier. Each multiplier input signal can be sent through a register independently
of other input signals. For example, you can send the multiplier Data Asignal through
a register and send the Data Bsignal directly to the multiplier.
The following control signals are available to each input register in the embedded
multiplier:
■
■
■
clock
clock enable
asynchronous clear
All input and output registers in a single embedded multiplier are fed by the same
clock, clock enable, and asynchronous clear signals.
Multiplier Stage
The multiplier stage of an embedded multiplier block supports 9 × 9 or 18 × 18
multipliers as well as other multipliers in between these configurations. Depending
on the data width or operational mode of the multiplier, a single embedded multiplier
can perform one or two multiplications in parallel. For multiplier information, refer to
“Operational Modes” on page 4–5.
Each multiplier operand is a unique signed or unsigned number. Two signals, signa
and signb, control an input of a multiplier and determine if the value is signed or
unsigned. If the signasignal is high, the Data Aoperand is a signed number. If the
signasignal is low, the Data Aoperand is an unsigned number.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
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