I/O Banks
Table 5–1 lists the differential I/O standards supported by each bank.
Table 5–1. Supported Differential I/O Types
Bank
Row I/O (Banks 1, 2, 5 and 6) (2)
Column I/O (Banks, 3, 4 and 7 through 12)
Data or
Regular I/O Clock Inputs
Pins
Data or
Clock
Outputs
Clock
Outputs
Type
Clock Inputs
Regular I/O
Pins
Differential HSTL
Differential SSTL
LVPECL
v
v
v
v
v
v
v
(1)
(1)
LVDS
v
v
v
v
v
v
v
HyperTransport
technology
Note to Table 5–1:
(1) Used as both inputs and outputs on the DQS/DQSn pins.
(2) Banks 5 and 6 are not available in Stratix II GX devices.
Table 5–2 shows the total number of differential channels available in
Stratix II devices. The available channels are divided evenly between the
left and right banks of the die. Non-dedicated clocks in the left and right
banks can also be used as data receiver channels. The total number of
receiver channels includes these four non-dedicated clock channels. Pin
migration is available for different size devices in the same package.
Table 5–2. Differential Channels in Stratix II Devices (Part 1 of 2) Notes (1), (2), and (3)
1,508-Pin
FineLine BGA
Within the
484-Pin
484-PinHybrid
672-Pin
780-Pin
1,020-Pin
Device
FineLine BGA FineLine BGA FineLine BGA FineLine BGA FineLine BGA
1,508-pin Fin
EP2S15
38 transmitters
42 receivers
38 transmitters
42 receivers
EP2S30
EP2S60
EP2S90
EP2S130
38 transmitters
42 receivers
58 transmitters
62 receivers
38 transmitters
42 receivers
58 transmitters
62 receivers
84 transmitters
84 receivers
38 transmitters
42 receivers
64 transmitters 90 transmitters 118transmitters
68 receivers 94 receivers 118 receivers
64 transmitters 88 transmitters 156transmitters
68 receivers 92 receivers 156 receivers
5–4
Altera Corporation
January 2008
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
