Specifications
When the register inputs/outputs parameter is turned off, the encoder
takes one clock cycle to encode a character. The encoded value—
corresponding to the values of datainand kinsampled by the encoder
on rising edge n—is output shortly after rising edge n, and is available to
be sampled on the rising edge of clock cycle n+1. (See Figure 3–6).
Figure 3–5. Encoder Timing Diagram—Three Cycle Latency
n
n+1 n+2 n+3
clk
datain, kin, en, idle_ins
dataout, rdout, kerr, valid
rdforce, rdin
a
b
c
d
a
b
e
b
c
f
g
d
e
c
d
e
f
a
a
b
c
d
e
f
rdcascade
Figure 3–6. Encoder Timing Diagram—One Cycle Latency
n
n+1
clk
datain, kin, en, idle_ins
dataout, rdout, kerr, valid
rdforce, rdin
a
a
b
a
b
c
b
d
c
d
e
d
e
f
g
e
f
f
c
g
a
b
c
d
e
f
g
rdcascade
Fibre Channel and IEEE 802.3z 1000BaseX
In Fibre Channel and IEEE 802.3z 1000BaseX applications the encoder
does not automatically select the correct 8-bit data for Fibre Channel EOF
or 1000BaseX Idle ordered sets. The running disparity based selection of
the correct 8-bit data must be made before passing the data to the encoder.
Altera Corporation
October 2007
MegaCore Version 7.2
3–7
8B10B Encoder/Decoder MegaCore Function User Guide
ALTERA [ ALTERA CORPORATION ]
