Functional Description
Figure 3–4. Cascaded Encoding Note (1)
clk
kerr
reset_n
kin [1]
dataout [9:0]
kin [1:0]
ena
valid
idle_ins
rdout
datain [15:8]
datain [15:0]
rdcascade
rdin
rdforce
clk
kerr
reset_n
kin [0]
dataout [9:0]
valid
ena
rdout
idle_ins
datain [7:0]
rdin
rdcascade
rdforce
Note to Figure 3–4:
(1) The ena, idle_ins, and rdforcesignals are set high (logic 1).
Encoding Latency
When the register inputs/outputsparameter is turned on, the
encoder is pipelined, thus it takes three clock cycles for a character to be
encoded. The encoded value—corresponding to the values of datain
and kinsampled by the encoder on rising edge n—is output shortly after
rising edge n+2, and is available to be sampled on the rising edge of clock
cycle n+3. (See Figure 3–5 on page 3–7). To enable cascaded encoding, the
data paths fed by the rdforceand rdininputs are not pipelined.
Because rdforceand rdinare normally only used in cascaded
configurations, this should not be a problem. In cases where the rdforce
and rdininputs are to be used in noncascaded configurations, they
should be delayed two clock cycles with respect to their corresponding
datainand kinvalues.
3–6
MegaCore Version 7.2
Altera Corporation
October 2007
8B10B Encoder/Decoder MegaCore Function User Guide
ALTERA [ ALTERA CORPORATION ]
