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5M80ZT64I4N 参数 Datasheet PDF下载

5M80ZT64I4N图片预览
型号: 5M80ZT64I4N
PDF下载: 下载PDF文件 查看货源
内容描述: MAX V器件手册 [MAX V Device Handbook]
分类和应用:
文件页数/大小: 166 页 / 4016 K
品牌: ALTERA [ ALTERA CORPORATION ]
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2–8  
Chapter 2: MAX V Architecture  
Logic Elements  
Logic Elements  
The smallest unit of logic in the MAX V architecture, the LE, is compact and provides  
advanced features with efficient logic utilization. Each LE contains a four-input LUT,  
which is a function generator that can implement any function of four variables. In  
addition, each LE contains a programmable register and carry chain with carry-select  
capability. A single LE also supports dynamic single-bit addition or subtraction mode  
that is selected by an LAB-wide control signal. Each LE drives all types of  
interconnects: local, row, column, LUT chain, register chain, and DirectLink  
interconnects as shown in Figure 2–6.  
Figure 2–6. LE for MAX V Devices  
Register chain  
routing from  
previous LE  
LAB-wide  
Synchronous  
Register Bypass  
LAB Carry-In  
Carry-In1  
Load  
Programmable  
Register  
LAB-wide  
Synchronous  
Packed  
Register Select  
addnsub  
Carry-In0  
Clear  
LUT chain  
routing to next LE  
data1  
Row, column,  
and DirectLink  
routing  
PRN/ALD  
data2  
data3  
Synchronous  
Load and  
Clear Logic  
Look-Up  
Table  
(LUT)  
Carry  
Chain  
D
Q
ADATA  
data4  
ENA  
CLRN  
Row, column,  
and DirectLink  
routing  
labclr1  
labclr2  
Asynchronous  
Clear/Preset/  
Load Logic  
Local routing  
labpre/aload  
Chip-Wide  
Reset (DEV_CLRn)  
Register chain  
output  
Register  
Feedback  
Clock and  
Clock Enable  
Select  
labclk1  
labclk2  
labclkena1  
labclkena2  
Carry-Out0  
Carry-Out1  
LAB Carry-Out  
You can configure each LE’s programmable register for D, T, JK, or SR operation. Each  
register has data, true asynchronous load data, clock, clock enable, clear, and  
asynchronous load/preset inputs. Global signals, general purpose I/O (GPIO) pins,  
or any LE can drive the registers clock and clear control signals. Either GPIO pins or  
LEs can drive the clock enable, preset, asynchronous load, and asynchronous data.  
The asynchronous load data input comes from the data3input of the LE. For  
combinational functions, the LUT output bypasses the register and drives directly to  
the LE outputs.  
Each LE has three outputs that drive the local, row, and column routing resources. The  
LUT or register output can drive these three outputs independently. Two LE outputs  
drive either a column or row and DirectLink routing connections while one output  
drives the local interconnect resources. This configuration allows the LUT to drive one  
output while the register drives another output. This register packing feature  
MAX V Device Handbook  
December 2010 Altera Corporation  
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