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5M80ZT64I4N 参数 Datasheet PDF下载

5M80ZT64I4N图片预览
型号: 5M80ZT64I4N
PDF下载: 下载PDF文件 查看货源
内容描述: MAX V器件手册 [MAX V Device Handbook]
分类和应用:
文件页数/大小: 166 页 / 4016 K
品牌: ALTERA [ ALTERA CORPORATION ]
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2–6  
Chapter 2: MAX V Architecture  
Logic Array Blocks  
LAB Interconnects  
Column and row interconnects and LE outputs within the same LAB drive the LAB  
local interconnect. Adjacent LABs, from the left and right, can also drive an LAB’s  
local interconnect through the DirectLink connection. The DirectLink connection  
feature minimizes the use of row and column interconnects, providing higher  
performance and flexibility. Each LE can drive 30 other LEs through fast local and  
DirectLink interconnects. Figure 2–4 shows the DirectLink connection.  
Figure 2–4. DirectLink Connection  
DirectLink interconnect from  
right LAB or IOE output  
DirectLink interconnect from  
left LAB or IOE output  
LE0  
LE1  
LE2  
LE3  
LE4  
LE5  
LE6  
LE7  
LE8  
LE9  
DirectLink  
interconnect  
to left  
DirectLink  
interconnect  
to right  
Local  
Interconnect  
Logic Element  
LAB  
LAB Control Signals  
Each LAB contains dedicated logic for driving control signals to its LEs. The control  
signals include two clocks, two clock enables, two asynchronous clears, a  
synchronous clear, an asynchronous preset/load, a synchronous load, and  
add/subtract control signals, providing a maximum of 10 control signals at a time.  
Synchronous load and clear signals are generally used when implementing counters  
but they can also be used with other functions.  
Each LAB can use two clocks and two clock enable signals. Each LAB’s clock and  
clock enable signals are linked. For example, any LE in a particular LAB using the  
labclk1signal also uses labclkena1. If the LAB uses both the rising and falling edges  
of a clock, it also uses both LAB-wide clock signals. Deasserting the clock enable  
signal turns off the LAB-wide clock.  
Each LAB can use two asynchronous clear signals and an asynchronous load/preset  
signal. By default, the Quartus II software uses a NOTgate push-back technique to  
achieve preset. If you disable the NOTgate push-back option or assign a given register  
to power-up high using the Quartus II software, the preset is then achieved using the  
asynchronous load signal with asynchronous load data input tied high.  
MAX V Device Handbook  
December 2010 Altera Corporation  
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