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5M80ZT100C5 参数 Datasheet PDF下载

5M80ZT100C5图片预览
型号: 5M80ZT100C5
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 14ns, PQFP100, 16 X 16 MM, 0.50 MM PITCH, TQFP-100]
分类和应用: 时钟可编程逻辑
文件页数/大小: 166 页 / 4004 K
品牌: ALTERA [ ALTERA CORPORATION ]
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2–4  
Chapter 2: MAX V Architecture  
Logic Array Blocks  
Figure 2–2 shows a floorplan of a MAX V device.  
Figure 2–2. Device Floorplan for MAX V Devices (Note 1)  
I/O Blocks  
I/O Blocks  
Logic Array  
Blocks  
Logic Array  
Blocks  
2 GCLK  
Inputs  
2 GCLK  
Inputs  
I/O Blocks  
UFM Block  
CFM Block  
Note to Figure 2–2:  
(1) The device shown is a 5M570Z device. 5M1270Z and 5M2210Z devices have a similar floorplan with more LABs. For 5M40Z, 5M80Z, 5M160Z,  
and 5M240Z devices, the CFM and UFM blocks are located on the left side of the device.  
Logic Array Blocks  
Each LAB consists of 10 LEs, LE carry chains, LAB control signals, a local interconnect,  
a look-up table (LUT) chain, and register chain connection lines. There are 26 possible  
unique inputs into an LAB, with an additional 10 local feedback input lines fed by LE  
outputs in the same LAB. The local interconnect transfers signals between LEs in the  
same LAB. LUT chain connections transfer the LUT output from one LE to the  
MAX V Device Handbook  
December 2010 Altera Corporation  
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