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5M80ZT100C5 参数 Datasheet PDF下载

5M80ZT100C5图片预览
型号: 5M80ZT100C5
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 14ns, PQFP100, 16 X 16 MM, 0.50 MM PITCH, TQFP-100]
分类和应用: 时钟可编程逻辑
文件页数/大小: 166 页 / 4004 K
品牌: ALTERA [ ALTERA CORPORATION ]
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2–2  
Chapter 2: MAX V Architecture  
Functional Description  
Figure 2–1 shows a functional block diagram of the MAX V device.  
Figure 2–1. Device Block Diagram  
IOE  
IOE  
IOE  
IOE  
IOE  
IOE  
Logic  
Element  
Logic  
Element  
Logic  
Element  
IOE  
IOE  
Logic  
Element  
Logic  
Element  
Logic  
Element  
Logic Array  
BLock (LAB)  
MultiTrack  
Interconnect  
Logic  
Element  
Logic  
Element  
Logic  
Element  
IOE  
Logic  
Element  
Logic  
Element  
Logic  
Element  
IOE  
MultiTrack  
Interconnect  
Each MAX V device contains a flash memory block within its floorplan. This block is  
located on the left side of the 5M40Z, 5M80Z, 5M160Z, and 5M240Z devices. On the  
5M240Z (T144 package), 5M570Z, 5M1270Z, and 5M2210Z devices, the flash memory  
block is located on the bottom-left area of the device. The majority of this flash  
memory storage is partitioned as the dedicated configuration flash memory (CFM)  
block. The CFM block provides the non-volatile storage for all of the SRAM  
configuration information. The CFM automatically downloads and configures the  
logic and I/O at power-up, providing instant-on operation.  
f For more information about configuration upon power-up, refer to the Hot Socketing  
and Power-On Reset for MAX V Devices chapter.  
A portion of the flash memory within the MAX V device is partitioned into a small  
block for user data. This user flash memory (UFM) block provides 8,192 bits of  
general-purpose user storage. The UFM provides programmable port connections to  
the logic array for reading and writing. There are three LAB rows adjacent to this  
block, with column numbers varying by device.  
MAX V Device Handbook  
December 2010 Altera Corporation  
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