Chapter 2: MAX V Architecture
2–7
Logic Array Blocks
With the LAB-wide addnsubcontrol signal, a single LE can implement a one-bit adder
and subtractor. This signal saves LE resources and improves performance for logic
functions such as correlators and signed multipliers that alternate between addition
and subtraction depending on data.
The LAB column clocks [3..0], driven by the global clock network, and LAB local
interconnect generate the LAB-wide control signals. The MultiTrack interconnect
structure drives the LAB local interconnect for non-global control signal generation.
The MultiTrack interconnect’s inherent low skew allows clock and control signal
distribution in addition to data signals. Figure 2–5 shows the LAB control signal
generation circuit.
Figure 2–5. LAB-Wide Control Signals
Dedicated
LAB Column
Clocks
4
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
labclkena2
labclkena1
syncload
labclr2
addnsub
Local
Interconnect
labclk1
labclk2
asyncload
or labpre
labclr1
synclr
December 2010 Altera Corporation
MAX V Device Handbook
ALTERA [ ALTERA CORPORATION ]
