5M1270ZT64A4N 参数 Datasheet PDF下载

型号：	5M1270ZT64A4N
PDF下载：	下载PDF文件查看货源
内容描述：	MAX V器件手册 [MAX V Device Handbook]
分类和应用：
文件页数/大小：	166 页 / 4016 K
品牌：	ALTERA [ ALTERA CORPORATION ]

2–18

Chapter 2: MAX V Architecture

MultiTrack Interconnect

The UFM block communicates with the logic array similar to LAB-to-LAB interfaces.

The UFM block connects to row and column interconnects and has local interconnect

regions driven by row and column interconnects. This block also has DirectLink

interconnects for fast connections to and from a neighboring LAB. For more

information about the UFM interface to the logic array, refer too “User Flash Memory

Block” on page 2–21.

Table 2–2 lists the MAX V device routing scheme.

Table 2–2. Routing Scheme for MAX V Devices

Destination

Source

LUT

UFM

Column Row Fast I/O

R4 (1) C4 (1)

Chain

(1)

—

(1)

—

Block

IOE

(1)

—

LUT Chain

—

Local

Interconnect

—

DirectLink

Interconnect

—

R4 Interconnect

C4 Interconnect

—

UFM Block

Column IOE

Row IOE

Note to Table 2–2:

(1) These categories are interconnects.

MAX V Device Handbook

December 2010 Altera Corporation

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