2–24
Chapter 2: Device Datasheet for Cyclone V Devices
Switching Characteristics
DQS Logic Block and Memory Output Clock Jitter Specifications
Table 2–27 lists the DQS phase shift error for Cyclone V devices.
Table 2–27. DQS Phase Shift Error Specification for DLL-Delayed Clock (tDQS_PSERR) for Cyclone V
Devices—Preliminary (1), (2)
Number of DQS Delay
Buffers
C6
C7, I7
Speed Grade
C8, A7
Speed Grade
Unit
Speed Grade
2
69
70
80
ps
Notes to Table 2–27:
(1) The numbers are preliminary pending silicon characterization.
(2) This error specification is the absolute maximum and minimum error. For example, skew on two DQS delay buffers
in a –7 speed grade is 70 ps or 35 ps.
(3) Delay chain engineering option setting: rb_co[1:0]=“11”.
Table 2–28 lists the memory output clock jitter specifications for Cyclone V devices.
Table 2–28. Memory Output Clock Jitter Specification for Cyclone V Devices—Preliminary (1), (2), (3)
C6
C7, I7
C8, A7
Clock
Network
Speed Grade
Speed Grade
Speed Grade
Parameter
Symbol
Unit
Min
Max
Min
Max
Min
Max
Clock period jitter
Regional
Regional
tJIT(per)
tJIT(cc)
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ps
ps
Cycle-to-cycle period
jitter
TBD
TBD
TBD
Duty cycle jitter
Regional
Global
tJIT(duty)
tJIT(per)
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ps
ps
Clock period jitter
Cycle-to-cycle period
jitter
Global
Global
tJIT(cc)
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ps
ps
Duty cycle jitter
tJIT(duty)
Notes to Table 2–28:
(1) Pending silicon characterization.
(2) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard.
(3) The clock jitter specification applies to the memory output clock pins generated using differential signal-splitter and DDIO circuits clocked by
a PLL output routed on a PHY, regional, or global clock network as specified. Altera recommends using PHY clock networks whenever possible.
OCT Calibration Block Specifications
Table 2–29 lists the OCT calibration block specifications for Cyclone V devices.
Table 2–29. OCT Calibration Block Specifications for Cyclone V Devices—Preliminary (Part 1 of 2)
Symbol
Description
Min
Typ
Max
Unit
OCTUSRCLK
Clock required by OCT calibration blocks
—
—
20
MHz
Number of OCTUSRCLK clock cycles required for
RS OCT /RT OCT calibration
TOCTCAL
—
1000
—
Cycles
Cyclone V Device Handbook
February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
ALTERA [ ALTERA CORPORATION ]
