2–22
Chapter 2: Device Datasheet for Cyclone V Devices
Switching Characteristics
High-Speed I/O Specification
Table 2–26 lists high-speed I/O timing for Cyclone V devices.
Table 2–26. High-Speed I/O Specifications for Cyclone V Devices—Preliminary (2), (3) (Part 1 of 2)
C6
C7, I7
Speed Grade
C8, A7
Speed Grade
Speed Grade
Symbol
Conditions
Unit
Min Typ
Max Min Typ
Max
Min Typ
Max
f
HSCLK_in (input
clock frequency)
True Differential I/O
Standards
Clock boost factor W = 1
5
—
437.5
5
—
420
5
—
320
MHz
(4)
to 40
fHSCLK_in (input
clock frequency)
Single Ended I/O
Standards
Clock boost factor W = 1
5
5
—
—
320
420
5
5
—
—
320
370
5
5
—
—
275
320
MHz
MHz
(4)
to 40
fHSCLK_OUT (output
clock frequency)
—
Transmitter
(5)
(5)
(5)
(5)
(5)
(5)
SERDES factor J = 4 to 10
—
—
840
—
—
740
—
—
640 Mbps
True Differential I/O
Standards - fHSDR
(data rate)
SERDES factor J = 1 to 2,
Uses DDR Registers
(7)
(7)
(7)
Mbps
Emulated
Differential I/O
Standards with
Three External
Output Resistor
Networks - fHSDR
(5)
(5)
(5)
SERDES factor J = 4 to 10
SERDES factor J = 4 to 10
—
—
640
170
—
—
640
170
—
—
550 Mbps
(6)
(data rate)
Emulated
Differential I/O
Standards with One
External Output
Resistor Network -
(5)
(5)
(5)
170 Mbps
(6)
fHSDR (data rate)
Total Jitter for Data Rate,
600 Mbps - 840 Mbps
—
—
—
—
160
0.1
—
—
—
—
160
0.1
—
—
—
—
160
0.1
ps
UI
tx Jitter - True
Differential I/O
Standards
Total Jitter for Data Rate,
< 600 Mbps
tx Jitter - Emulated
Differential I/O
Standards with
Three External
Output Resistor
Networks
Total Jitter for Data Rate
< 640 Mbps
—
—
—
—
TBD (1)
—
—
—
—
TBD (1)
—
—
—
—
TBD (1)
UI
UI
tx Jitter - Emulated
Differential I/O
Standards with One
External Output
Resistor Network
Total Jitter for Data Rate
< 640 Mbps
TBD (1)
TBD (1)
TBD (1)
Cyclone V Device Handbook
February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
ALTERA [ ALTERA CORPORATION ]
