2–16
Chapter 2: Device Datasheet for Cyclone V Devices
Switching Characteristics
Table 2–20. Transceiver Specifications for Cyclone V GX Devices—Preliminary (Part 3 of 3)
C6
C7, I7
C8, A7
Symbol/
Description
Speed Grade
Speed Grade
Speed Grade
Conditions
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Transmitter
Supported I/O
Standards
1.5 V PCML
Data rate
VOCM
—
—
614
—
—
—
—
—
30
30
—
650
85
3125
—
614
—
—
—
—
—
30
30
—
650
85
3125
—
614
—
—
—
—
—
30
30
—
650
85
2500
—
Mbps
mV
Ω
85−Ω setting
100−Ω setting
120−Ω setting
150-Ω setting
—
—
—
—
100
120
150
—
—
100
120
150
—
—
100
120
150
—
—
Ω
Differential on-chip
termination resistors
—
—
—
Ω
—
—
—
Ω
(6)
Rise time
160
160
160
160
160
160
ps
(6)
Fall time
—
—
—
—
ps
CMU PLL
Supported data range
—
614
—
3125
614
—
3125
614
—
2500
Mbps
Transceiver-FPGA Fabric Interface
Interface speed
—
25
25
—
—
187.5
25
25
—
—
163.84
163.84
25
25
—
—
156.25
156.25
MHz
MHz
(single-width mode)
Interface speed
—
163.84
(double-width mode)
Notes to Table 2–20:
(1) Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table.
(2) The reference clock common mode voltage is equal to the VCCR_GXB power supply level.
(3) The device cannot tolerate prolonged operation at this absolute maximum.
(4) The differential eye opening specification at the receiver input pins assumes that you have disabled the Receiver Equalization feature. If you enable the
Receiver Equalization feature, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.
(5) The rate matcher supports only up to 300 parts per million (ppm).
(6) The Quartus II software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.
Cyclone V Device Handbook
February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
ALTERA [ ALTERA CORPORATION ]
