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5CGXC4 参数 Datasheet PDF下载

5CGXC4图片预览
型号: 5CGXC4
PDF下载: 下载PDF文件 查看货源
内容描述: 旋风V器件手册 [Cyclone V Device Handbook]
分类和应用:
文件页数/大小: 74 页 / 1776 K
品牌: ALTERA [ ALTERA CORPORATION ]
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2–20  
Chapter 2: Device Datasheet for Cyclone V Devices  
Switching Characteristics  
Table 2–23. PLL Specifications for Cyclone V Devices—Preliminary (1) (Part 3 of 3)  
Symbol  
tDRIFT  
Parameter  
Min  
Typ  
Max  
10  
Unit  
Frequency drift after PFDENA is disabled for a duration of  
100 µs  
%
dKBIT  
Bit number of Delta Sigma Modulator (DSM)  
Numerator of Fraction  
24  
Bits  
kVALUE  
TBD (1) 8388608 TBD (1)  
fRES  
Resolution of VCO frequency (fINPFD =100 MHz)  
5.96  
Hz  
Notes to Table 2–23:  
(1) Pending silicon characterization.  
(2) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O  
standard.  
(3) This specification is limited by the lower of the two: I/O fMAX or FOUT of the PLL.  
(4) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source < 120 ps.  
(5) FREF is fIN/N when N = 1.  
(6) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies  
to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a  
different measurement method and are available in Table 2–28 on page 2–24.  
(7) The cascaded PLL specification is only applicable with the following condition:  
a. Upstream PLL: 0.59 MHz Upstream PLL BW < 1 MHz  
b. Downstream PLL: Downstream PLL BW > 2 MHz  
(8) High bandwidth PLL settings are not supported in external feedback mode.  
(9) External memory interface clock output jitter specifications use a different measurement method, which is available in Table 2–28 on page 2–24.  
DSP Block Specifications  
Table 2–24 lists the Cyclone V DSP block performance specifications.  
Table 2–24. DSP Block Performance Specifications for Cyclone V Devices—Preliminary  
Performance  
Mode  
Unit  
C6  
C7, I7  
Speed Grade  
C8, A7  
Speed Grade  
Speed Grade  
Modes using One DSP Block  
Independent 9 x 9 Multiplication  
Independent 18 x 19 Multiplication  
Independent 18 x 18 Multiplication  
Independent 27 x 27 Multiplication  
Independent 18 x 25 Multiplication  
Independent 20 x 24 Multiplication  
Two 18 x 19 Multiplier Adder Mode  
18 x 18 Multiplier Added Summed with 36-bit Input  
Modes using Two DSP Blocks  
340  
287  
287  
250  
310  
310  
310  
310  
300  
250  
250  
200  
250  
250  
250  
250  
260  
200  
200  
160  
200  
200  
200  
200  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
Complex 18 x 19 multiplication  
Two 27 x 27 Multiplier Adder  
310  
250  
310  
250  
200  
250  
200  
160  
200  
MHz  
MHz  
MHz  
Four 18 x 19 Multiplier Adder  
Cyclone V Device Handbook  
February 2012 Altera Corporation  
Volume 1: Device Overview and Datasheet