Chapter 2: Device Datasheet for Cyclone V Devices
2–15
Switching Characteristics
Table 2–20. Transceiver Specifications for Cyclone V GX Devices—Preliminary (Part 2 of 3)
C6
C7, I7
C8, A7
Symbol/
Description
Speed Grade
Speed Grade
Speed Grade
Conditions
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Transceiver Clocks
fixedclkclock
frequency
Avalon® Memory-
Mapped (Avalon-MM)
PHY management clock
frequency
PCIe
Receiver Detect
—
125
—
—
125
—
—
125
—
MHz
MHz
< 150
Receiver
Supported I/O
Standards
1.5 V PCML, 2.5 V PCML, LVPECL, and LVDS
Data rate
—
—
614
—
—
—
3125
1.2
614
—
—
—
3125
1.2
614
—
—
—
2500
1.2
Mbps
V
Absolute VMAX for a
receiver pin (3)
Absolute VMIN for a
receiver pin
—
—
–0.4
—
—
—
—
–0.4
—
—
—
—
–0.4
—
—
—
—
V
V
Maximum peak-to-peak
differential input voltage
VID (diff p-p) before
1.6
1.6
1.6
device configuration
Maximum peak-to-peak
differential input voltage
VID (diff p-p) after
—
—
—
85
—
—
2.2
—
—
85
—
—
2.2
—
—
85
—
—
2.2
—
V
device configuration
Minimum differential
eye opening at the
receiver serial input
mV
(4)
pins
85−Ω setting
100−Ω setting
120−Ω setting
150-Ω setting
—
—
—
—
85
—
—
—
—
—
—
—
—
85
—
—
—
—
—
—
—
—
85
—
—
—
—
Ω
Ω
Ω
Ω
100
120
150
100
120
150
100
120
150
Differential on-chip
termination resistors
Differential and
common mode return
loss
PCIe Gen1,
GIGE
Compliant
—
Programmable PPM
detector (5)
—
—
—
62.5, 100, 125, 200, 250, 300, 500, and 1000
ppm
UI
Run Length
—
—
—
—
200
4
—
—
—
—
200
4
—
—
—
—
200
4
Programmable
equalization
dB
DC Gain Setting
= 0
—
—
0
3
—
—
—
—
0
3
—
—
—
—
0
3
—
—
dB
dB
Programmable DC gain
DC Gain Setting
= 1
February 2012 Altera Corporation
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
ALTERA [ ALTERA CORPORATION ]
