AV-51002
2017.02.10
1-56
DLL Frequency Range Specifications
Figure 1-6: LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate Less than 1.25 Gbps
Sinusoidal Jitter Amplitude
20db/dec
0.1 UI
P-P
Frequency
20 MHz
baud/1667
DLL Frequency Range Specifications
Table 1-43: DLL Frequency Range Specifications for Arria V Devices
Parameter
–I3, –C4
–I5, –C5
–C6
Unit
DLL operating frequency range
200 – 667
200 – 667
200 – 667
MHz
DQS Logic Block Specifications
Table 1-44: DQS Phase Shift Error Specifications for DLL-Delayed Clock (tDQS_PSERR) for Arria V Devices
is error specification is the absolute maximum and minimum error.
Number of DQS Delay Buffer
–I3, –C4
–I5, –C5
–C6
Unit
2
40
80
80
ps
Arria V GX, GT, SX, and ST Device Datasheet
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