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5ASXMB3E4F31I3N 参数 Datasheet PDF下载

5ASXMB3E4F31I3N图片预览
型号: 5ASXMB3E4F31I3N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 670MHz, PBGA896, ROHS COMPLIANT, FBGA-896]
分类和应用: 时钟LTE可编程逻辑
文件页数/大小: 184 页 / 1809 K
品牌: ALTERA [ ALTERA CORPORATION ]
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AV-51002  
2017.02.10  
2-33  
10G PCS Data Rate  
PMA Width  
20  
40  
20  
20  
9
16  
32  
16  
16  
10  
20  
10  
10  
8
8
Transceiver  
Speed Grade  
Mode (164)  
PCS/Core Width  
16  
8
2
3
C3, I3L  
core speed grade  
9.9  
7.92  
7.2  
4.9  
4.,5  
3.92  
3.6  
Register  
C4, I4  
core speed grade  
8.8  
8.2  
7.04  
6.56  
4.4  
4.1  
3.52  
3.28  
Related Information  
Operating Conditions on page 2-1  
10G PCS Data Rate  
Table 2-31: 10G PCS Approximate Maximum Data Rate (Gbps) for Arria V GZ Devices  
PMA Width  
PCS Width  
64  
64  
40  
40  
40  
32  
32  
32  
Transceiver Speed  
Grade  
Mode (165)  
66/67  
12.5  
50  
40  
64/66/67  
2
3
2
3
C3, I3L core speed  
grade  
12.5  
10.69  
12.5  
10.88  
10.88  
FIFO  
C4, I4 core speed  
grade  
10.3125  
12.5  
10.3125  
12.5  
10.69  
10.69  
10.69  
10.3125  
12.5  
9.92  
10.88  
9.92  
9.92  
C3, I3L core speed  
grade  
10.88  
9.92  
Register  
C4, I4 core speed  
grade  
10.3125  
10.3125  
10.3125  
(164)  
(165)  
e Phase Compensation FIFO can be configured in FIFO mode or register mode. In the FIFO mode, the pointers are not fixed, and the latency can  
vary. In the register mode the pointers are fixed for low latency.  
e Phase Compensation FIFO can be configured in FIFO mode or register mode. In the FIFO mode, the pointers are not fixed, and the latency can  
vary. In the register mode the pointers are fixed for low latency.  
Arria V GZ Device Datasheet  
Send Feedback  
Altera Corporation  
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