AV-51002
2017.02.10
2-31
Clock Network Data Rate
Transceiver Speed Grade 2
Transceiver Speed Grade 3
Symbol/Description
Conditions
Unit
Min
Typ
Max
Min
Typ
Max
Supported data range
—
600
—
3250/
600
—
3250/
Mbps
3125(158)
3125 (158)
(159)
tpll_powerdown
—
—
1
—
—
—
10
1
—
—
—
10
µs
µs
(160)
tpll_lock
—
Related Information
Arria V Device Overview
For more information about device ordering codes.
Clock Network Data Rate
Table 2-29: Clock Network Maximum Data Rate Transmitter Specifications
Valid data rates below the maximum specified in this table depend on the reference clock frequency and the PLL counter settings. Check the
MegaWizard message during the PHY IP instantiation.
ATX PLL
CMU PLL (161)
Bonded
fPLL
Clock Network
Non-bonded
Mode (Gbps) Mode (Gbps)
Bonded
Channel
Span
Non-bonded
Channel
Span
Non-bonded
Mode (Gbps) Mode (Gbps)
Bonded
Channel
Span
Mode (Gbps) Mode (Gbps)
x1 (162)
x6 (162)
x6 PLL Feedback (163)
12.5
—
—
6
6
12.5
—
—
6
6
3.125
—
—
3
12.5
12.5
12.5
12.5
3.125
—
6
—
Side-wide
—
Side-wide
—
—
(158)
(159)
(160)
(161)
(162)
(163)
When you use fPLL as a TXPLL of the transceiver.
tpll_powerdown is the PLL powerdown minimum pulse width.
tpll_lock is the time required for the transmitter CMU/ATX PLL to lock to the input reference clock frequency afer coming out of reset.
ATX PLL is recommended at 8 Gbps and above data rates for improved jitter performance.
Channel span is within a transceiver bank.
Side-wide channel bonding is allowed up to the maximum supported by the PHY IP.
Arria V GZ Device Datasheet
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