AV-51002
2017.02.10
2-32
Standard PCS Data Rate
Clock Network
ATX PLL
Bonded
CMU PLL (161)
Bonded
fPLL
Non-bonded
Channel
Span
Non-bonded
Channel
Span
Non-bonded
Bonded
Mode (Gbps) Mode (Gbps)
Channel
Span
Mode (Gbps) Mode (Gbps)
Mode (Gbps) Mode (Gbps)
xN (PCIe)
—
8.0
8.0
8
—
5.0
8
—
—
—
8.0
Up to 13
channels
above and
below PLL
Up to 13
channels
above
and
below
PLL
Up to 13
channels
above and
below PLL
—
8.01 to
9.8304
Up to 7
channels
above
and
below
PLL
xN (Native PHY IP)
7.99
7.99
3.125
3.125
Standard PCS Data Rate
Table 2-30: Standard PCS Approximate Maximum Date Rate (Gbps) for Arria V GZ Devices
e maximum data rate is also constrained by the transceiver speed grade. Refer to the “Commercial and Industrial Speed Grade Offering for Arria
V GZ Devices” table for the transceiver speed grade.
PMA Width
20
40
20
20
9
16
32
16
16
10
20
10
10
8
8
8
Transceiver
Speed Grade
Mode (164)
PCS/Core Width
16
2
3
C3, I3L
core speed grade
9.9
7.84
7.2
5.3
4.7
4.24
3.76
FIFO
C4, I4
core speed grade
8.8
8.2
7.2
6.56
4.8
4.3
3.84
3.44
(161)
(164)
ATX PLL is recommended at 8 Gbps and above data rates for improved jitter performance.
e Phase Compensation FIFO can be configured in FIFO mode or register mode. In the FIFO mode, the pointers are not fixed, and the latency can
vary. In the register mode the pointers are fixed for low latency.
Arria V GZ Device Datasheet
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