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5AGXMA3D631C4N 参数 Datasheet PDF下载

5AGXMA3D631C4N图片预览
型号: 5AGXMA3D631C4N
PDF下载: 下载PDF文件 查看货源
内容描述: 阿里亚V器件概述 [Arria V Device Overview]
分类和应用:
文件页数/大小: 37 页 / 793 K
品牌: ALTERA [ ALTERA CORPORATION ]
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AV-51001  
2013.05.06  
7
Package Plan  
Package Plan  
Table 5: Package Plan for Arria V GX DevicesPreliminary  
F672  
F8964  
F1152  
F1517  
(40 mm)  
Member  
Code  
(27 mm)  
(35 mm)  
(31 mm)  
GPIO  
336  
336  
336  
336  
XCVR  
GPIO  
416  
416  
384  
384  
384  
384  
XCVR  
GPIO  
XCVR  
GPIO  
XCVR  
A1  
A3  
A5  
A7  
B1  
B3  
B5  
B7  
9
9
9
24  
24  
24  
24  
24  
24  
9
9
18  
18  
18  
18  
544  
544  
544  
544  
544  
544  
9
704  
704  
704  
704  
24  
24  
36  
36  
Arria V GT  
This section provides the available options, maximum resource counts, and package plan for the Arria V GT  
devices.  
Available Options  
Figure 2: Sample Ordering Code and Available Options for Arria V GT DevicesPreliminary  
Transceiver Count  
Package Type  
Embedded Hard IPs  
Maximum channels  
F
:
FineLine BGA (FBGA)  
Operating Temperature  
Industrial (TJ = -40° C to 100° C)  
M
:
1 hard PCIe and 2 hard  
memory controllers  
D
G
H
K
:
:
:
:
9
18  
24  
36  
F
:
Maximum 2 hard PCIe and  
4 hard memory controllers  
I
:
Family Signature  
5A : Arria V  
5A  
GT  
F
D7  
K
3
F
40  
I
3
N
Optional Suffix  
Indicates specific device  
options or shipment method  
Family Variant  
Package Code  
GT : 10-Gbps transceivers  
27 : 672 pins  
31 : 896 pins  
35 : 1,152 pins  
40 : 1,517 pins  
N
:
Lead-free packaging  
ES : Engineering sample  
FPGA Fabric  
Member Code  
C3 : 156K logic elements  
C7 : 242K logic elements  
D3 : 362K logic elements  
D7 : 504K logic elements  
Transceiver  
Speed Grade  
Speed Grade  
3
: 10.3125 Gbps  
3 (fastest)  
5
4
In the F896 package, the PCIe hard IP block on the right side of the Arria V GX A5, A7, B1, and B3 devices  
support x1 for Gen1 and Gen2 data rates.  
Arria V Device Overview  
Altera Corporation  
Feedback  
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