AV-51001
2013.05.06
37
Document Revision History
Date
Version
Changes
November 2011
1.1
• Updated Table 1–1, Table 1–2, Table 1–3, Table 1–4, Table 1–6, Table
1–7, Table 1–9, and Table 1–10.
• Added “SoC FPGA with HPS” section.
• Updated “Clock Networks and PLL Clock Sources” and “Ordering
Information” sections.
• Updated Figure 1–5.
• Added Figure 1–6.
• Minor text edits.
August 2011
1.0
Initial release.
Arria V Device Overview
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