AV-51001
2013.05.06
30
SoC FPGA with HPS
Protocol
Data Rates
(Gbps)
Transmitter Data Path Features
Receiver Data Path Features
XAUI
3.125 to 4.25 • Phase compensation FIFO
• Byte serializer
• Word aligner
• Deskew FIFO
• 8B/10B encoder
• Bit-slip
• Channel bonding
• XAUI state machine for
bonding four channels
• Rate match FIFO
• 8B/10B decoder
• Byte deserializer
• Byte ordering
• XAUI state machine for
realigning four channels
SRIO
1.25 to 6.25 • Phase compensation FIFO
• Byte serializer
• Word aligner
• Deskew FIFO
• Rate match FIFO
• 8B/10B decoder
• Byte deserializer
• 8B/10B encoder
• Bit-slip
• Channel bonding
• SRIO V2.1-compliant x2 and • Byte ordering
x4 channel bonding
• SRIO V2.1-compliant x2 and
x4 deskew state machine
SoC FPGA with HPS
Each SoC FPGA combines an FPGA fabric and an HPS in a single device. This combination delivers the
flexibility of programmable logic with the power and cost savings of hard IP in these ways:
• Reduces board space, system power, and bill of materials cost by eliminating a discrete embedded processor
• Allows you to differentiate the end product in both hardware and software, and to support virtually any
interface standard
• Extends the product life and revenue through in-field hardware and software updates
HPS Features
The HPS consists of a dual-core ARM Cortex-A9 MPCore processor, a rich set of peripherals, and a shared
multiport SDRAM memory controller, as shown in the following figure.
Arria V Device Overview
Altera Corporation
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