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5AGXMA1D431C3ES 参数 Datasheet PDF下载

5AGXMA1D431C3ES图片预览
型号: 5AGXMA1D431C3ES
PDF下载: 下载PDF文件 查看货源
内容描述: 阿里亚V器件概述 [Arria V Device Overview]
分类和应用:
文件页数/大小: 37 页 / 793 K
品牌: ALTERA [ ALTERA CORPORATION ]
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AV-51001  
2013.05.06  
34  
Enhanced Configuration and Configuration via Protocol  
capability reduces the size of the device because it allows multiple applications on a single devicesaving  
the board space and reducing the power consumption.  
Altera simplifies the time-intensive task of partial reconfiguration by building this capability on top of the  
proven incremental compile and design flow in the Quartus II design software. With the Altera® solution,  
you do not need to know all the intricate device architecture details to perform a partial reconfiguration.  
Partial reconfiguration is supported through the FPP x16 configuration interface. You can seamlessly use  
partial reconfiguration in tandem with dynamic reconfiguration to enable simultaneous partial reconfiguration  
of both the device core and transceivers.  
Enhanced Configuration and Configuration via Protocol  
Table 23: Configuration Modes and Features of Arria V Devices  
Arria V devices support 1.8 V, 2.5 V, 3.0 V, and 3.3 V26 programming voltages and several configuration modes.  
Mode  
Data  
Width  
Max Clock Max Data Decompression Design Se-  
Partial  
Remote  
System  
Update  
Rate  
Rate  
curity  
Reconfiguration27  
(MHz)  
(Mbps)  
AS through the EPCS 1 bit, 4  
100  
Yes  
Yes  
Yes  
Yes  
and EPCQ serial  
bits  
configuration device  
PS through CPLD or  
external  
microcontroller  
1 bit  
125  
125  
Yes  
8 bits  
16 bits  
32 bits29  
125  
125  
100  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes28  
Parallel flash  
loader  
FPP  
CvP (PCIe)  
x1, x2, x4,  
and x8  
lanes  
Yes  
JTAG  
1 bit  
33  
33  
Yes28  
16 bits  
32 bits  
125  
100  
Yes  
Yes  
Yes  
Yes  
Configuration via  
HPS  
Parallel flash  
loader  
Instead of using an external flash or ROM, you can configure the Arria V devices through PCIe using CvP.  
The CvP mode offers the fastest configuration rate and flexibility with the easy-to-use PCIe hard IP block  
26  
27  
Arria V GZ does not support 3.3 V.  
Partial reconfiguration is an advanced feature of the device family. If you are interested in using partial recon-  
figuration, contact Altera for support.  
Supported at a clock rate of 50-62.5 MHz.  
Arria V GZ only  
28  
29  
Arria V Device Overview  
Altera Corporation  
Feedback  
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