2–32
Chapter 2: Device Datasheet for Arria V Devices
Switching Characteristics
Table 2–29. High-Speed I/O Specifications for Arria V Devices—Preliminary (1), (2), (3) (Part 2 of 3)
–4 Speed Grade
–5 Speed Grade
–6 Speed Grade
Symbol
Conditions
Unit
Min Typ
Max
Min Typ
Max
Min Typ
Max
Transmitter
(7)
(7)
(7)
(7)
(7)
(7)
True
SERDES factor J = 3 to 10
—
—
1250
—
—
1250
—
—
1050
Mbps
Mbps
Differential
I/O Standards
- fHSDR (data
rate)
SERDES factor J = 1 to 2, Uses
DDR Registers
(7)
(7)
(7)
Emulated
Differential
I/O Standards
with Three
External
(7)
(7)
(7)
SERDES factor J = 4 to 10
—
TBD
—
TBD
—
TBD
Mbps
Output
Resistor
Networks -
fHSDR (data
(8)
rate)
Total Jitter for Data Rate,
600 Mbps - 1.25 Gbps
—
—
—
—
—
—
160
0.1
—
—
—
—
—
—
160
0.1
—
—
—
—
—
—
160
0.1
ps
UI
ps
tx Jitter - True
Differential
I/O Standards
Total Jitter for Data Rate,
< 600 Mbps
tx Jitter
-
Total Jitter for Data Rate,
600 Mbps – 1.25 Gbps
TBD
TBD
TBD
Emulated
Differential
I/O Standards
with Three
External
Total Jitter for Data Rate
< 600 Mbps
—
—
TBD
—
—
TBD
—
—
TBD
UI
Output
Resistor
Network
TX output clock duty cycle for both
True and Emulated Differential I/O
Standards
tDUTY
45
—
—
50
—
—
55
45
—
—
50
—
—
55
45
—
—
50
—
—
55
%
ps
ps
True Differential I/O Standards
200
250
200
250
200
300
Emulated Differential I/O
Standards with Three External
Output Resistor Networks
tRISE & tFALL
True Differential I/O Standards
—
—
—
—
150
300
—
—
—
—
150
300
—
—
—
—
150
300
ps
ps
TCCS
Emulated Differential I/O
Standards
Arria V Device Handbook
February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
ALTERA [ ALTERA CORPORATION ]
