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5AGTMB1D431I4N 参数 Datasheet PDF下载

5AGTMB1D431I4N图片预览
型号: 5AGTMB1D431I4N
PDF下载: 下载PDF文件 查看货源
内容描述: 阿里亚V器件手册 [Arria V Device Handbook]
分类和应用:
文件页数/大小: 82 页 / 1787 K
品牌: ALTERA [ ALTERA CORPORATION ]
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2–28  
Chapter 2: Device Datasheet for Arria V Devices  
Switching Characteristics  
(1)  
Table 2–25. PLL Specifications for Arria V Devices—Preliminary  
(Part 2 of 3)  
Symbol  
tLOCK  
tDLOCK  
Parameter  
Min  
Typ  
Max  
Unit  
Time required to lock from end-of-device configuration or  
1
ms  
deassertion of areset  
Time required to lock dynamically (after switchover or  
reconfiguring any non-post-scale counters/delays)  
1
ms  
PLL closed-loop low bandwidth  
10  
0.3  
1.5  
4
MHz  
MHz  
fCLBW  
PLL closed-loop medium bandwidth  
(8)  
PLL closed-loop high bandwidth  
MHz  
tPLL_PSERR  
tARESET  
Accuracy of PLL phase shift  
50  
ps  
Minimum pulse width on the aresetsignal  
Input clock cycle-to-cycle jitter (FREF 100 MHz)  
Input clock cycle-to-cycle jitter (FREF < 100 MHz)  
Period jitter for dedicated clock output (FOUT 100 MHz)  
Period jitter for dedicated clock output (FOUT < 100 MHz)  
ns  
0.15  
+750  
UI (p-p)  
ps (p-p)  
ps (p-p)  
mUI (p-p)  
(4), (5)  
tINCCJ  
(1)  
TBD  
TBD  
(6)  
tOUTPJ_DC  
(1)  
(1)  
Cycle-to-cycle jitter for dedicated clock output  
(FOUT 100 MHz)  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
ps (p-p)  
mUI (p-p)  
ps (p-p)  
(6)  
tOUTCCJ_DC  
Cycle-to-cycle jitter for dedicated clock output  
(FOUT < 100 MHz)  
(1)  
(1)  
(1)  
(1)  
(1)  
Period Jitter for clock output on the regular I/O  
(FOUT 100 MHz)  
(6),  
tOUTPJ_IO  
(9)  
Period Jitter for clock output on the regular I/O  
(FOUT < 100 MHz)  
mUI (p-p)  
ps (p-p)  
Cycle-to-cycle jitter for clock output on the regular I/O  
(FOUT 100 MHz)  
(6),  
tOUTCCJ_IO  
(9)  
Cycle-to-cycle jitter for clock output on the regular I/O  
(FOUT < 100 MHz)  
mUI (p-p)  
tOUTPJ_DC_F  
Period jitter for dedicated clock output in fractional mode  
TBD (1)  
TBD (1)  
Cycle-to-cycle jitter for dedicated clock output in fractional  
mode  
tOUTCCJ_DC_F  
tOUTPJ_IO_F  
tOUTCCJ_IO_F  
Period Jitter for clock output on the regular I/O in fractional  
mode  
TBD (1)  
TBD (1)  
Cycle-to-cycle jitter for clock output on the regular I/O in  
fractional mode  
Period jitter for dedicated clock output in cascaded PLLs  
(FOUT 100 MHz)  
(1)  
TBD  
ps (p-p)  
mUI (p-p)  
%
tCASC_OUTPJ_DC  
(6), (7)  
Period jitter for dedicated clock output in cascaded PLLs  
(FOUT < 100 MHz)  
(1)  
TBD  
Frequency drift after PFDENA is disabled for a duration of  
100 µs  
tDRIFT  
10  
Arria V Device Handbook  
February 2012 Altera Corporation  
Volume 1: Device Overview and Datasheet  
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