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5AGTMB1D431I4N 参数 Datasheet PDF下载

5AGTMB1D431I4N图片预览
型号: 5AGTMB1D431I4N
PDF下载: 下载PDF文件 查看货源
内容描述: 阿里亚V器件手册 [Arria V Device Handbook]
分类和应用:
文件页数/大小: 82 页 / 1787 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 2: Device Datasheet for Arria V Devices  
2–33  
Switching Characteristics  
Table 2–29. High-Speed I/O Specifications for Arria V Devices—Preliminary (1), (2), (3) (Part 3 of 3)  
–4 Speed Grade  
Min Typ Max  
–5 Speed Grade  
Min Typ Max  
–6 Speed Grade  
Symbol  
Conditions  
Unit  
Min Typ  
Max  
Receiver  
True  
Differential  
I/O Standards  
- fHSDRDPA  
(data rate)  
SERDES factor J = 3 to 10  
SERDES factor J = 3 to 10  
1250  
1250  
1050  
Mbps  
(7)  
(7)  
(9)  
(7)  
(7)  
(7)  
(9)  
(7)  
(7)  
(7)  
(9)  
(7)  
Mbps  
Mbps  
fHSDR (data  
SERDES factor J = 1 to 2, Uses  
DDR Registers  
rate)  
DPA Mode  
DPA run  
length  
10000  
300  
10000  
300  
10000  
300  
UI  
Soft CDR mode  
Soft-CDR  
ppm tolerance  
ppm  
ps  
Non DPA Mode  
Sampling  
Window  
300  
300  
300  
Notes to Table 2–29:  
(1) When J = 3 to 10, use the serializer/deserializer (SERDES) block.  
(2) When J = 1 or 2, bypass the SERDES block.  
(3) This applies to LVDS source synchronous mode only.  
(4) This applies to DPA and soft-CDR modes only.  
(5) Clock Boost Factor (W) is the ratio between the input data rate and the input clock rate.  
(6) This is achieved by using the LVDS clock network.  
(7) The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or local) that  
you use. The I/O differential buffer and input register do not have a minimum toggle rate.  
(8) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin, transmitter  
channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.  
(9) You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board skew margin,  
transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.  
Figure 2–1 shows the DPA lock time specifications with the DPA PLL calibration  
option enabled.  
Figure 2–1. DPA Lock Time Specification with DPA PLL Calibration Enabled  
rx_reset  
DPA Lock Time  
rx_dpa_locked  
256 data  
transitions  
96 slow  
clock cycles  
256 data  
transitions  
96 slow  
clock cycles  
256 data  
transitions  
February 2012 Altera Corporation  
Arria V Device Handbook  
Volume 1: Device Overview and Datasheet  
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