1–20
Chapter 1: Overview for the Arria V Device Family
Ordering Information
Ordering Information
This section describes the ordering information for Arria V devices.
Figure 1–5 and Figure 1–6 show the ordering codes for Arria V devices.
Figure 1–5. Ordering Information for Arria V GX and GT Devices
PackageType
Transceiver Count
Embedded Hard IPs
F
: FineLine BGA (FBGA)
D
E
: 9
: 12
B
: No hard PCIe or hard
memory controller
G : 18
OperatingTemperature
M : 1 hard PCIe and 2 hard
memory controller
H
K
: 24
: 36
C
I
: Commercial temperature (TJ = 0° C to 85° C)
: Industrial temperature (TJ = -40° C to 100° C)
F
: Maximum 2 hard PCIe and
4 hard memory controllers
Optional Suffix
Indicates specific device
options or shipment method
Family Signature
5A GX
M
A5
G
4
F
31
C
4
N
5A : Arria V
N
: Lead-free packaging
ES : Engineering sample
FPGA Fabric Speed Grade
Family Variant
GX : 6-Gbps transceivers
GT : 10-Gbps transceivers
Package Code
GX Variant
4 (fastest)
FBGA PackageType
27 : 672 pins
31 : 896 pins
Member Code
GX Variant
5
6
Transceiver Speed Grade
GX Variant
35 : 1,152 pins
40 : 1,517 pins
A1: 75K logic elements
A3: 149K logic elements
A5: 190K logic elements
A7: 243K logic elements
B1: 300K logic elements
B3: 362K logic elements
B5: 420K logic elements
B7: 503K logic elements
GT Variant
GT Variant
5
4
6
: 6-Gbps
: 3-Gbps
GT Variant
: 10-Gbps
3
D3: 362K logic elements
D7: 503K logic elements
Arria V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
