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5AGTMB1D431I4N 参数 Datasheet PDF下载

5AGTMB1D431I4N图片预览
型号: 5AGTMB1D431I4N
PDF下载: 下载PDF文件 查看货源
内容描述: 阿里亚V器件手册 [Arria V Device Handbook]
分类和应用:
文件页数/大小: 82 页 / 1787 K
品牌: ALTERA [ ALTERA CORPORATION ]
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1–16  
Chapter 1: Overview for the Arria V Device Family  
Enhanced Configuration and Configuration via Protocol  
Enhanced Configuration and Configuration via Protocol  
Arria V devices support 3.3-V programming voltage and the following configuration  
modes:  
active serial (AS)  
passive serial (PS)  
fast passive parallel (FPP)  
CvP  
Configuration via HPS  
configuration through JTAG  
You can configure Arria V devices through PCIe using CvP instead of an external  
flash or ROM. The CvP mode offers the fastest configuration rate and flexibility with  
the easy-to-use PCIe hard IP block interface. The Arria V CvP implementation  
conforms to the PCIe 100-ms power-up-to-active time requirement.  
f
For more information regarding CvP, refer to the Configuration via Protocol (CvP)  
Implementation in Altera FPGAs User Guide.  
Table 1–11 lists the configuration modes that Arria V devices support.  
Table 1–11. Configuration Modes and Features for Arria V Devices  
Maximum  
Clock Rate  
(MHz)  
Maximum  
Data Rate Decompression  
(Mbps)  
Remote  
System  
Update  
Design  
Security  
Partial  
Reconfiguration  
Mode  
Data Width (Bit)  
AS  
PS  
1, 4  
1
100  
125  
v
v
v
v
v
125  
Parallel  
flash loader  
FPP  
CvP  
HPS  
8, 16  
125  
33  
v
v
v
v
v
v
16-bit only  
x1, x2, x4, x8 (1)  
v
v
v
Parallel  
32  
1
125  
33  
flash loader  
JTAG  
Note to Table 1–11:  
(1) Number of lanes instead of bits.  
Power Management  
Arria V devices leverage FPGA architectural features and process technology  
advancements to reduce the total device core power consumption by as much as 50%  
when compared with Stratix IV devices at the same performance level.  
Additionally, Arria V devices have a number of hard IP blocks that not only reduce  
logic resources but also deliver substantial power savings when compared with soft  
implementations. The list includes PCIe Gen1 and Gen2, XAUI, GbE, SRIO, GPON  
and CPRI protocols. The hard IP blocks consume up to 25% less power than  
equivalent soft implementations.  
Arria V Device Handbook  
Volume 1: Device Overview and Datasheet  
February 2012 Altera Corporation  
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