MAX 5000 Programmable Logic Device Family Data Sheet
Figure 7. MAX 5000 Timing Model
Single-LAB EPLDs
Shared Expander
Delay
tSEXP
Logic Array
Control Delay
tLAC
Register
Delay
Input
Delay
tIN
Logic Array
Delay
tLAD
Output
Delay
tOD
tXZ
tZX
tRD
tCOMB
tLATCH
tCLR
tPRE
tSU
Global
Clock Delay
tICS
tH
I/O
Delay
tIO
Array Clock
Delay
tIC
Feedback
Delay
tFD
Multi-LAB EPLDs
Shared Expander
Delay
tSEXP
Logic Array
Control Delay
tLAC
Register
Delay
Input
Delay
tIN
Logic Array
Delay
tLAD
tRD
9
tCOMB
tLATCH
tCLR
tPRE
tSU
Output
Delay
tOD
Global Clock
Delay
tICS
tH
tXZ
tZX
Array Clock
Delay
PIA
Delay
tPIA
tIC
Feedback
Delay
tFD
I/O
Delay
tIO
Altera Corporation
721
ALTERA [ ALTERA CORPORATION ]
