MAX 5000 Programmable Logic Device Family Data Sheet
Table 8. EPM5064, EPM5128, EPM5130 & EPM5192 MAX 5000 Device Capacitance
Symbol
Parameter
Conditions
Min
Max
Unit
CIN
Input pin capacitance
I/O pin capacitance
VIN = 0 V, f = 1.0 MHz
VOUT = 0 V, f = 1.0 MHz
10
20
pF
pF
CI/O
Notes to tables:
(1) See the Operating Requirements for Altera Devices Data Sheet in this data book.
(2) Minimum DC input is –0.3 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 7.0 V for
input currents less than 100 mA and periods shorter than 20 ns.
(3) Numbers in parentheses are for industrial-temperature-range devices.
(4) Maximum VCC rise time for MAX 5000 devices is 10 ms.
(5) Typical values are for TA = 25° C and VCC = 5.0 V.
(6) The IOH parameter refers to high-level TTL output current; the IOL parameter refers to low-level TTL output current.
Figure 6 shows typical output drive characteristics of MAX 5000 devices.
Figure 6. Output Drive Characteristics of MAX 5000 Devices
250
IOL
200
VCCINT = 5.0 V
VCCIO = 5.0 V
Room Temperature
150
Typical IO
Output
Current (mA)
100
50
IOH
2
3
3.8 4
5
1
VO Output Voltage (V)
MAX 5000 EPLD timing can be analyzed with the MAX+PLUS II
software, with a variety of other industry-standard EDA simulators and
timing analyzers, or with the timing model shown in Figure 7. MAX 5000
EPLDs have fixed internal delays that allow the designer to determine the
worst-case timing for any design. The MAX+PLUS II software provides
timing simulation, point-to-point delay prediction, and detailed timing
analysis for system-level performance evaluation.
Timing Model
720
Altera Corporation
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