AS7C4096A
®
Write waveform 2 (CE controlled)9
tWC
tWR
tAH
tAW
Address
tAS
tCW
CE
tWP
WE
DIN
tDW
Data valid
tDH
AC test conditions
- Output load: see Figure B.
- Input pulse level: GND to V - 0.5V. See Figures A and B.
CC
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
+5.0V
Thevenin equivalent:
168
480Ω
Ω
V
- 0.5V
GND
DOUT
255
CC
90%
10%
90%
10%
+1.728V
DOUT
Ω
C10
2 ns
Figure A: Input pulse
GND
Figure B: 5.0V Output load
Notes
1
2
3
4
5
6
7
8
9
During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
For test conditions, see AC Test Conditions.
tCLZ and tCHZ are specified with CL = 5pF as in Figure B. Transition is measured ±500 mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE is HIGH for read cycle.
CE and OE are LOW for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
All write cycle timings are referenced from the last valid address to the first transitioning address.
10 C = 30pF, except at high Z and low Z parameters, where C = 5pF.
5/27/05, v. 1.1
Alliance Semiconductor
P. 6 of 10
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
