March 2004
AS7C3513B
®
3.3V 32K×16 CMOS SRAM
Features
• Industrial and commercial temperature
• Organization: 32,768 words × 16 bits
• Center power and ground pins
• High speed
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
• 44-pin JEDEC standard package
• 400 mil SOJ
• 10/12/15/20 ns address access time
• 5, 6, 7, 8 ns output enable access time
• Low power consumption: ACTIVE
• 288 mW / max @ 10 ns
• 400 mil TSOP 2
• ESD protection > 2000 volts
• Latch-up current > 200 mA
• Low power consumption: STANDBY
• 18 mW / max CMOS
• 6T 0.18m CMOS Technology
Logic block diagram
Pin arrangement
A0
A1
A2
44-Pin SOJ, TSOP 2 (400 mil)
V
CC
32K × 16
Array
GND
NC
A3
A2
A1
A0
CE
1
2
3
4
5
6
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A5
A6
OE
UB
LB
A3
A4
A5
A6
A7
I/O0
7
8
9
I/O15
I/O14
I/O13
I/O12
GND
I/O1
I/O2
I/O3
I/O0–I/O7
I/O8–I/O15
I/O
buffer
Control circuit
10
11
12
13
14
15
16
17
18
19
20
21
22
V
CC
GND
I/O4
I/O5
I/O6
I/O7
WE
A14
A13
A12
A11
NC
V
CC
Column decoder
I/O11
I/O10
I/O9
I/O8
NC
A7
A8
A9
A10
NC
WE
UB
OE
LB
CE
Selection guide
-10
10
5
-12
-15
-20
20
8
Unit
ns
Maximum address access time
12
6
15
7
Maximum output enable access time
Maximum operating current
ns
80
5
75
5
70
5
65
5
mA
mA
Maximum CMOS standby current
3/24/04, v.1.2
Alliance Semiconductor
P. 1 of 10
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