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AS7C3513B-15TCN 参数 Datasheet PDF下载

AS7C3513B-15TCN图片预览
型号: AS7C3513B-15TCN
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3V 32K ×16的CMOS SRAM [3.3V 32K x 16 CMOS SRAM]
分类和应用: 存储内存集成电路静态存储器光电二极管
文件页数/大小: 10 页 / 218 K
品牌: ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
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AS7C3513B  
®
AC test conditions  
- Output load: see Figure B.  
Thevenin equivalent:  
- Input pulse level: GND to 3.0V. See Figure A.  
- Input rise and fall times: 2 ns. See Figure A.  
- Input and output timing reference levels: 1.5V.  
168Ω  
Dout  
+1.728V  
+3.3V  
320Ω  
Dout  
350Ω  
+3.0V  
C13  
90%  
10%  
90%  
10%  
2 ns  
Figure A: Input pulse  
GND  
GND  
Figure B: 3.3V Output load  
Notes  
1
2
3
4
5
6
7
8
9
During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.  
This parameter is sampled, but not 100% tested.  
For test conditions, see AC Test Conditions, Figures A and B.  
These parameters are specified with CL = 5pF, as in Figure B. Transition is measured ±500mV from steady-state voltage.  
This parameter is guaranteed, but not 100% tested.  
WE is High for read cycle.  
CE and OE are Low for read cycle.  
Address valid prior to or coincident with CE transition Low.  
All read cycle timings are referenced from the last valid address to the first transitioning address.  
10 Not applicable.  
11 All write cycle timings are referenced from the last valid address to the first transitioning address.  
12 Not applicable.  
13 C=30pF, except on High Z and Low Z parameters, where C=5pF.  
3/24/04, v.1.2  
Alliance Semiconductor  
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