AUGUST 2010
AS6C8016A
512K X 16 BIT LOW POWER CMOS SRAM
,
L
o
w
P
o
6 8
w
e
r
V
1
6
B
F
a
m
i
y
3)
AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference)
Input Pulse Level : 0.4 to 2.4V
VTM
2)
R1
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : 1.5V
1)
Output Load (See right) : CL = 100pF+ 1 TTL(70nsec)
1)
CL = 30pF + 1 TTL(45ns/55ns)
1. Including scope and Jig capacitance
2)
R2
1)
CL
2. R =3070Ω,
R =3150Ω
2
1
3. V =2.8V
TM
4. CL = 5pF + 1 TTL (measurement with t , t , t
, t
, t
)
LZ HZ OLZ OHZ WHZ
o
o
READ CYCLE (V =2.7 to 3.6V, Gnd = 0V, T = -40 C to +85 C)
cc
A
55ns
Max
Symbol
Parameter
Unit
Min
Read cycle time
tRC
tAA
55
-
ns
ns
ns
ns
ns
ns
Address access time
-
-
-
55
55
35
45
-
Chip select to output
tCO
tOE
tBA
Output enable to valid output
UB, LB access time
Chip select to low-Z output
tLZ
5
tBLZ
tOLZ
tHZ
UB, LB enable to low-Z output
Output enable to low-Z output
5
5
-
-
ns
ns
ns
ns
ns
ns
Chip disable to high-Z output
0
20
20
20
-
tBHZ
tOHZ
tOH
0
UB, LB disable to how-Z output
Output disable to high-Z output
0
Output hold from address change
10
o
o
WRITE CYCLE (V =2.7 to 3.6V, Gnd = 0V, T = -40 C to +85 C)
cc
A
55ns
Symbol
Parameter
Write cycle time
Unit
Min
Max
tWC
tCW
tAS
55
-
ns
ns
ns
ns
ns
ns
Chip select to end of write
Address setup time
45
0
-
-
-
Address valid to end of write
tAW
tBW
tWP
tWR
tWHZ
tDW
tDH
45
UB, LB valid to end of write
Write pulse width
45
45
0
-
-
Write recovery time
-
ns
ns
ns
ns
ns
Write to ouput high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
0
20
25
0
-
-
tOW
5
M
n
n
M
M
7
s
-
U
i
4
-
6
-
n
4
2
4
2
n
5
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
