AUGUST 2010
AS6C8016A
512K X 16 BIT LOW POWER CMOS SRAM
,
S
V
F
i
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)
t
WC
Address
CS
t
(2)
t
(4)
CW
WR
t
AW
t
BW
UB,LB
WE
t
(1)
t
(3)
WP
AS
t
DH
t
DW
Data in
Data Valid
High-Z
High-Z
Data out
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting
UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest
transition when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS or WE going high.
8
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
