AS4LC8M8S0
AS4LC4M16S0
®
I
specifications and conditions
DD
(0° C ≤ T ≤ 70° C, V , V
= +3.3V ± 0.3V)
A
DD DDQ
Max
–8
Parameter
Operating current: active mode; burst = 2; READ or WRITE;
RC = tRC(min); CAS latency = 3
Symbol
IDD1
–75
115
–10F/ 10 Units Notes
95
2
95
2
mA
mA
mA
mA
mA
4, 5
4,5
t
Standby current: power-down mode; all banks idle;
CKE = low
IDD2
IDD3
IDD4
IDD5
2
Standby current: active mode; CKE = high; CS# = high; all
banks active after tRCD met; no accesses in progress
45
35
35
4, 5
4,5
Operating current: burst mode; continuous burst; READ or
WRITE; all banks active; CAS latency = 3
140
210
130
210
120
190
tRFC = tRFC(min);
4, 5
CL = 3
Auto refresh current: CKE = high;
CS# = high
tRFC = 15.625ms;
CL = 3
IDD6
IDD7
50
1
50
1
40
1
mA
mA
4,5
4,5
Self-refresh current: CKE ≤ 0.2V
Notes
1
2
3
4
5
I
specifications are tested after proper initialization of the device.
DD
I
is dependent on output loading and clock cycle time. Values are specified with minimum cycle time and outputs open.
DD
I
tests have V = 0V and V = 3V.
IL IH
current will decrease at lower CAS latencies. This is because the lower the latency, the lower the clock cycle time.
DD
I
DD
Address transitions average one transition every two clock cycles.
7/ 5/ 00
ALLIANCE SEMICONDUCTOR
7
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
