AS4LC8M8S0
AS4LC4M16S0
®
AC parameters common to all waveforms (continued)
-75
-8
-10 F
-10
CAS
Sym
Parameter
latency Min Max Min
Max
–
Min
Max
–
Min
1
Max Unit Notes
tDQD
DQM to input data delay
1
0
–
–
1
0
1
0
–
–
CLK
CLK
tDQM DQM to data mast during writes
–
–
0
DQM to data high Z during
tDQZ
2
–
2
–
2
–
2
–
CLK
reads
Write command to input data
tDWD
0
5
1
–
–
–
0
5
1
–
–
–
0
5
1
–
–
–
0
5
1
–
–
–
CLK
CLK
CLK
delay
tDAL
Data-in to active command
Load mode register to active/
refresh command
tMRD
3
2
3
2
–
–
3
2
–
–
3
2
–
–
3
2
–
–
CLK
CLK
4
4
Data-out high Z from
precharge/ burst stop command
tROH
CKE to CLOCK disable or power-
down entry mode
tCKED
1
1
–
–
1
1
–
–
1
1
–
–
1
1
–
–
CLK
CLK
CKE to clock enable or power-
down exit mode
tPED
Notes
1
2
3
4
5
6
7
Minimum clock cycles = (Minimum time / clock cycle time) rounded up.
Minimum delay required to complete write.
Column address change allowed every cycle.
Parameters dependent on CAS latency.
If clock rising time > 1ns, (tr/ 2-0.5)ns should be added to parameter.
If (tr and tf) > 1ns, [(tr+tf)/ 2-1]ns should be added to parameter.
Outputs measured at 1.5V with 50pF load only without resistive termination.
Burst sequence
(BL = 4)
Initial address
A1
0
A0
0
Sequential
Interleave
0
1
2
3
1
2
3
0
1
3
0
1
2
0
1
2
3
1
0
3
2
2
3
0
1
3
2
1
0
0
1
2
3
0
1
0
1
1
Burst sequence
(BL = 8)
Initial address
A2
0
A1
0
A0
Sequential
Interleave
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
1
3
4
5
6
7
0
1
2
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
1
0
3
2
5
4
7
6
2
3
0
1
6
7
4
5
3
2
1
0
7
6
5
4
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
0
0
2
3
4
5
6
7
0
6
7
0
1
2
3
4
0
1
0
1
1
0
1
0
1
1
1
1
7/ 5/ 00
ALLIANCE SEMICONDUCTOR
9
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
