AS4LC8M8S0
AS4LC4M16S0
®
Pin descriptions
Pin
Name
Description
All operations synchronized to rising edge of CLK. It also increments
the burst counters.
CLK
System clock
Controls CLK input. If CKE is high, the next CLK rising edge is valid.
If CKE is low, the internal clock is suspended from the next clock
cycle and the burst address and output states are frozen. Pulling CKE
low has the following effects:
all banks idle: Precharge power down and Self refresh.
row active in any bank: Active power down.
CKE
Clock enable
burst/ access in progress: Clock suspend.
When in Power down or Self refresh mode, CKE becomes
asynchronous until exiting the mode.
Enables or disables device operation by masking or enabling all inputs
except CLK, CKE, UDQM/ LDQM (×16), DQM (×8).
CS
Chip select
Address
Row and column addresses are multiplexed. Row address: A0~A11.
Column address (8M×8): A0~A8. Column address (4M×16):
A0~A7.
A0~A11
Memory cell array is organized in 4 banks. BA0 and BA1 select which
internal bank will be active during activate, read, write, and
precharge operations.
BA0, BA1
RAS
Bank select
Enables row access and precharge operation. When RAS is low, row
address is latched at the rising edge of CLK.
Row address strobe
Enables column access. When CAS is low, starting column address for
the burst access operation is latched at the rising edge of the CLK.
CAS
WE
Column address strobe
Write enable
Enables write operation and row precharge operation.
Controls I/ O buffers. When DQM is high, output buffers are disabled
during a read operation and input data is masked during a write
operation. DQM latency is 2 clocks for Read and 0 clocks for Write.
For ×16, LDQM controls lower byte (DQ0–7) and UDQM controls
upper byte (DQ8–15). For ×8, only one DQM controls the 8 DQs.
UDQM and LDQM are considered same state when referenced as
DQM.
×8: DQM
×16: UDQM/ LDQM
Output disable/ write
mask
Data inputs/ outputs are multiplexed. Data bus for 8M×8 is
DQ0~DQ7 only.
DQ0~DQ15
VDD/ VSS
Data input/ output
Power supply/ ground Power and ground for core logic and input buffers.
Data output power/
VDDQ/ VSSQ
Power and ground for data output buffers.
ground
7/ 5/ 00
ALLIANCE SEMICONDUCTOR
3
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
