AS4C8M16D1
Table 15. Electrical AC Characteristics
(VDD = 2.5V 5%, TA = -40~85 C)
-5
Symbol
Parameter
Unit
Min
7.5
6
Max
12
CL=2
CL=2.5
CL = 3
ns
ns
ns
tCK
tCK
tCK
Clock cycle time
12
5
12
tCH
tCL
Clock high level width
Clock low level width
0.45
0.45
0.55
0.55
tDQSCK DQS-out access time from CK,
-0.6
-0.7
0.6
0.7
ns
ns
CK
tAC
Output access time from CK,
CK
tDQSQ DQS-DQ Skew
-
0.4
ns
tCK
tCK
tCK
ns
tRPRE Read preamble
0.9
1.1
tRPST Read postamble
0.4
0.6
tDQSS CK to valid DQS-in
tWPRES DQS-in setup time
tWPRE DQS write preamble
tWPST DQS write postamble
tDQSH DQS in high level pulse width
tDQSL DQS in low level pulse width
0.72
1.25
0
-
0.25
-
tCK
tCK
tCK
tCK
0.4
0.6
0.35
-
0.35
-
Fast slew rate
Slow slew rate
Fast slew rate
Slow slew rate
0.6
-
tIS
tIH
Address and Control input setup time
Address and Control input hold time
0.7
-
ns
0.6
-
0.7
-
tDS
DQ & DM setup time to DQS
DQ & DM hold time to DQS
Clock half period
0.4
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDH
0.4
-
tHP
tCLMIN or tCHMIN
-
tQH
DQ/DQS output hold time from DQS
Row cycle time
tHP - tQHS
-
tRC
60
70
-
tRFC
tRAS
tRCD
tRP
Refresh row cycle time
-
Row active time
40
70K
Active to Read or Write delay
Row precharge time
18
-
-
-
-
-
18
tRRD
tWR
Row active to Row active delay
Write recovery time
10
15
tMRD
tCCD
tDAL
tXSRD
tPDEX
tREFI
tIPW
tDIPW
Mode register set cycle time
Col. Address to Col. Address delay
2
tCK
tCK
tCK
tCK
ns
s
ns
ns
1
Auto precharge write recovery + Precharge time
Self refresh exit to read command delay
Power down exit time
7
-
200
tCK + tIS
-
-
-
15.6
-
Refresh interval time
Control and Address input pulse width
DQ & DM input pulse width (for each input)
2.2
1.75
-
tHZ
Data-out high-impedance window from CK,
-
0.7
ns
CK
tLZ
Data-out low-impedance window from CK,
Data Hold Skew Factor
-0.7
-
0.7
0.5
-
ns
ns
CK
tQHS
tDSS
tDSH
DQS falling edge to CK rising – setup time
DQS falling edge to CK rising – hold time
0.2
0.2
tCK
tCK
-
Alliance Memory Inc. Confidential
12
Rev. 1.1
Feb. /2009
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
