AS4C8M16D1
Table 14. D.C. Characteristics
(VDD = 2.5V 5%, TA = -40~85 C)
Parameter & Test Condition
OPERATING CURRENT: One bank; Active-Precharge; t =t (min);
-5
Symbol
Unit
Max.
RC RC
IDD0
120
mA
t =t (min); DQ,DM and DQS inputs changing once per clock cycle;
CK CK
Address and control inputs changing once every two clock cycles.
OPERATING CURRENT : One bank; Active-Read-Precharge; BL=4;
IDD1
140
10
mA
mA
t
=t (min); t =t (min); lout=0mA; Address and control inputs changing
CK CK
RC RC
once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;
power-down mode; t =t (min); CKE=LOW
IDD2P
CK CK
IDLE STANDLY CURRENT : CKE = HIGH;
=HIGH(DESELECT); All
CS
banks idle; t =t (min); Address and control inputs changing once per
IDD2N
IDD3P
IDD3N
50
40
80
mA
mA
mA
CK CK
clock cycle; V =V
for DQ, DQS and DM
IN
REF
ACTIVE POWER-DOWN STANDBY CURRENT : one bank active; power-
down mode; CKE=LOW; t =t (min)
CK CK
ACTIVE STANDBY CURRENT :
=HIGH;CKE=HIGH; one bank active ;
CS
=t (max);t =t (min);Address and control inputs changing once per
t
RC RC
CK CK
clock cycle; DQ,DQS,and DM inputs changing twice per clock cycle
OPERATING CURRENT BURST READ : BL=2; READS; Continuous burst;
IDD4R
180
180
mA
mA
one bank active; Address and control inputs changing once per clock cycle;
t =t (min); lout=0mA;50% of data changing on every transfer
CK CK
OPERATING CURRENT BURST Write : BL=2; WRITES; Continuous
Burst ;one bank active; address and control inputs changing once per clock
IDD4W
IDD5
cycle; t =t (min); DQ,DQS,and DM changing twice per clock cycle; 50%
CK CK
of data changing on every transfer
AUTO REFRESH CURRENT : t =t
(min); t =t (min)
200
4
mA
mA
RC RFC
CK CK
≦
SELF REFRESH CURRENT: Self Refresh Mode ; CKE 0.2V;t =t (min) IDD6
CK CK
BURST OPERATING CURRENT 4 bank operation:
Four bank interleaving READs; BL=4;with Auto Precharge; t =t (min);
RC RC
IDD7
300
mA
t =t (min); Address and control inputs change only during Active, READ ,
CK CK
or WRITE command
Figure 3: Timing Waveform for IDD7 Measurement at 200 MHz CK Operation
CK
CK
tRCD
READ
AP
READ
AP
READ
AP
READ
AP
ACT
ACT
ACT
ACT
ACT
COMMAND
ADDRESS
...pattern repeats...
Bank 1
Row e
Bank 0
Row d
Bank 2
Row f
Bank 1
Col e
Bank 3
Row g
Bank 0
Row h
Bank 3
Col c
Bank 0
Col d
Bank 2
Col f
CL=3
DQS
DQ
D0 a
D0 a D0 a D0 b
D0 a
D0 b D0 b D0 b
D0 d D0 d
D0 e
D0 e
D0 f
D0 f
D0 c D0 c D0 c D0 c
D0 d D0 d D0 e
D0 e
Alliance Memory Inc. Confidential
11
Rev. 1.1
Feb. /2009
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
