AS4C64M8D2
Timing Waveforms
Figure 7. Initialization sequence after power-up
tCH tCL
CK
CK#
tIS
CKE
ODT
tIS
EMR
S
ANY
CMD
EMR
S
EMR
S
PRE
ALL
PRE
ALL
REF
REF
MRS
NOP
MRS
Command
Follow OCD Flowchart
tRFC
400ns
tRP
tMRD
tMRD
tRP
tRFC
tMRD
tOIT
OCD
OCD
DLL
ENABLE
DLL
CAL.MOD
E EXIT
Default
min 200 Cycle
RESET
NOTE 1: To guarantee ODT off, VREF must be valid and a LOW level must be applied to the ODT pin.
Figure 8. ODT update delay timing-tMOD
EMRS
NOP
NOP
NOP
NOP
NOP
CMD
CK#
CK
ODT
tIS
tMOD, max
Updating
tAOFD
tMOD, min
Rtt
Old setting
New setting
NOTE 1: To prevent any impedance glitch on the channel, the following conditions must be met:
- tAOFD must be met before issuing the EMRS command.
- ODT must remain LOW for the entire duration of tMOD window, until tMOD, max is met.
then the ODT is ready for normal operation with the new setting, and the ODT signal may be raised again to turned
on the ODT.
NOTE 2: EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt (Nominal).
NOTE 3: "setting" in this diagram is the Register and I/O setting, not what is measured from outside.
Figure 9. ODT update delay timing-tMOD, as measured from outside
CK#
CK
EMRS
NOP
NOP
NOP
NOP
NOP
CMD
ODT
tIS
tAOND
tAOFD
tMOD, max
Rtt
Old setting
New setting
NOTE 1: EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt (Nominal).
NOTE 2: "setting" in this diagram is measured from outside.
Confidential
33
Rev. 1.0
Feb. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
