AS4C64M8D2
Table 28. Input clock jitter spec parameter
-25
-3
Parameter
Clock period jitter
Symbol
Units Notes
Min.
-100
-80
Max.
100
80
Min.
-125
-100
-250
-200
-175
-225
-250
-250
-350
-450
-125
Max.
125
100
250
200
175
225
250
250
350
450
125
tJIT (per)
tJIT (per,lck)
tJIT (cc)
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
33
33
33
33
33
33
33
33
33
33
33
Clock period jitter during DLL locking
period
Cycle to cycle clock period jitter
-200
-160
-150
-175
-200
-200
-300
-450
-100
200
160
150
175
200
200
300
450
100
Cycle to cycle clock period jitter during
DLL locking period
Cumulative error across 2 cycles
tJIT (cc,lck)
tERR (2per)
tERR (3per)
tERR (4per)
tERR (5per)
tERR (6-10per)
tERR (11-50per)
tJIT (duty)
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across n cycles,
n=6...10, inclusive
Cumulative error across n cycles,
n=11...50, inclusive
Duty cycle jitter
NOTE 34: These parameters are specified per their average values, however it is understood that the following
relationship between the average timing and the absolute instantaneous timing holds at all times. (Min and
max of SPEC values are to be used for calculations in the table below.)
Table 29. Absolute clock period average values
Parameter
Symbol
Min.
Max.
Unit
Absolute clock period
tCK (abs)
tCK(avg),min + tJIT(per),min
tCK(avg),max + tJIT(per),max
ps
Absolute clock HIGH pulse width
Absolute clock LOW pulse width
tCH (abs)
tCL (abs)
tCH(avg),min * tCK(avg),min + tCH(avg),max * tCK(avg),max + ps
tJIT(duty),min tJIT(duty),max
tCL(avg),min * tCK(avg),min + tCL(avg), max * tCK(avg),max + ps
tJIT(duty),min tJIT(duty), max
NOTE 35: tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not
an input specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing tQH. The
value to be used for tQH calculation is determined by the following equation;
tHP = Min ( tCH(abs), tCL(abs) ),
where,
tCH(abs) is the minimum of the actual instantaneous clock HIGH time;
tCL(abs) is the minimum of the actual instantaneous clock LOW time;
NOTE 36: tQHS accounts for:
1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is
transferred to the output; and
2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
Confidential
31
Rev. 1.0
Feb. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
