AS4C64M8D2
Figure 13.ODT timing mode switch at exit power-down mode
T0
T1
T4
T5
T6
T7
T8
T9
T10
T11
CK#
CK
tIS
tAXPD
VIH(ac)
CKE
Exiting from Slow Active Power Down Mode or Precharge power Down Mode.
tIS
ODT
VIL(ac)
Active & Standby mode
tAOFD
timings to be applied.
Internal
Term Res.
RTT
tIS
ODT
Power Down mode
VIL(ac)
timings to be applied.
tAOFPD max
Internal
Term Res.
RTT
tIS
VIH(ac)
Active & Standby mode
ODT
timings to be applied.
tAOND
RTT
Internal
Term Res.
tIS
VIH(ac)
Power Down mode
ODT
timings to be applied.
tAONPD max
Internal
Term Res.
RTT
Figure 14. Bank activate command cycle (tRCD=3, AL=2, tRP=3, tRRD=2, tCCD=2)
T0
T1
T2
T3
Tn
Tn+1
Tn+2
Tn+3
CK#
CK
Internal RAS# - CAS# delay (>=tRCD min
)
Bank A
Row Addr.
Bank A
Col. Addr.
Bank B
Row Addr.
Bank B
Col. Addr
Bank A
Addr.
Bank B
Addr.
Bank A
Row Addr.
ADDRESS
CAS# - CAS# delay time (tCCD
)
Additive latency delay (AL)
tRCD = 1
Read Begins
RAS# - RAS# delay time (>=tRRD
)
Bank A
Post CAS#
Read
Bank B
Post CAS#
Read
Bank A
Activate
Bank B
Activate
Bank A
Precharge
Bank B
Precharge
Bank A
Activate
COMMAND
Bank precharge time (>=tRP
)
Bank Active (>=tRAS
)
RAS# Cycle time (>=tRC
)
Confidential
36
Rev. 1.0
Feb. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
