AS4C64M8D2
Table 24. IDD specification parameters and test conditions
(VDD = 1.8V 0.1V, TOPER = 0~95 C)
-25
-3
Parameter & Test Condition
Symbol
Unit
Max.
Operating one bank active-precharge current:
tCK =tCK (min), tRC = tRC (min), tRAS = tRAS(min); CKE is HIGH, CS# is
HIGH between valid commands; Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
IDD0
75
70
mA
Operating one bank active-read-precharge current:
IOUT = 0mA; BL = 4, CL = CL (min), AL = 0; tCK = tCK (min),tRC = tRC (min),
tRAS = tRAS(min), tRCD = tRCD (min);CKE is HIGH, CS# is HIGH between
valid commands; Address bus inputs are switching; Data pattern is same
as IDD4W
IDD1
85
80
mA
Precharge power-down current:
IDD2P
8
8
mA
mA
All banks idle;tCK =tCK (min); CKE is LOW; Other control and address bus
inputs are STABLE; Data bus inputs are FLOATING
Precharge quiet standby current:
All banks idle; tCK =tCK (min); CKE is HIGH, CS# is HIGH; Other control
and address bus inputs are STABLE; Data bus inputs are FLOATING
Precharge standby current:
IDD2Q
35
35
All banks idle; tCK = tCK (min); CKE is HIGH, CS# is HIGH; Other control
and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
IDD2N
IDD3P
IDD3N
40
40
mA
Active power-down current:
All banks open; tCK =tCK (min); CKE is LOW; Other control
20
14
MRS(A12)=0
20
14
mA
mA
and address bus inputs are STABLE; Data bus inputs are
MRS(A12)=1
FLOATING
Active standby current:
All banks open; tCK = tCK(min), tRAS = tRAS (max), tRP = tRP (min); CKE is
HIGH, CS# is HIGH between valid commands; Other control and address
bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst write current:
All banks open, continuous burst writes; BL = 4, CL = CL (min), AL = 0;
tCK= tCK (min), tRAS = tRAS (max), tRP = tRP (min); CKE is HIGH, CS# is
HIGH between valid commands; Address bus inputs are switching; Data
bus inputs are switching
55
55
mA
mA
IDD4W
120
110
Operating burst read current:
All banks open, continuous burst reads, IOUT = 0mA; BL = 4, CL = CL
(min), AL = 0; tCK = tCK (min), tRAS = tRAS (max), tRP = tRP (min); CKE is
HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
IDD4R
130
120
mA
Burst refresh current:
tCK = tCK (min); refresh command at every tRFC (min) interval; CKE is
HIGH, CS# is HIGH between valid commands; Other control and address
bus inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current:
CK and CK# at 0V; CKE ≤ 0.2V;Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
IDD5
95
6
90
6
mA
mA
IDD6
Operating bank interleave read current:
All bank interleaving reads, IOUT= 0mA; BL = 4, CL = CL (min), AL =tRCD
(min) - 1 x tCK (min); tCK = tCK (min), tRC = tRC (min), tRRD = tRRD (min), tRCD
= tRCD (min); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are STABLE during DESELECTs. Data pattern is
same as IDD4R
IDD7
200
180
mA
Confidential
23
Rev. 1.0
Feb. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
