AS4C64M8D2
Power-Down
Power-down is synchronously entered when CKE is registered LOW along with NOP or Deselect command. No
read or write operation may be in progress when CKE goes LOW. These operations are any of the following: read
burst or write burst and recovery. CKE is allowed to go LOW while any of other operations such as row activation,
precharge or autoprecharge, mode register or extended mode register command time, or auto refresh is in
progress.
The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset after exiting
power-down mode for proper read operation.
If power-down occurs when all banks are precharged, this mode is referred to as Precharge Power-down; if
power-down occurs when there is a row active in any bank, this mode is referred to as Active Power-down. For
Active Power-down two different power saving modes can be selected within the MRS register, address bit A12.
When A12 is set to “LOW” this mode is referred as “standard active power-down mode” and a fast power-down
exit timing defined by the tXARD timing parameter can be used. When A12 is set to “HIGH” this mode is referred as
a power saving “LOW power active power-down mode”. This mode takes longer to exit from the power-down
mode and the tXARDS timing parameter has to be satisfied. Entering power-down deactivates the input and output
buffers, excluding CK, CK#, ODT and CKE. Also the DLL is disabled upon entering precharge power-down or
slow exit active power-down, but the DLL is kept enabled during fast exit active power-down. In power-down
mode, CKE LOW and a stable clock signal must be maintained at the inputs of the DDR2 SDRAM, and all other
input signals are “Don’t Care”. Power-down duration is limited by 9 times tREFI of the device.
The power-down state is synchronously exited when CKE is registered HIGH (along with a NOP or Deselect
command). A valid, executable command can be applied with power-down exit latency, tXP, tXARD or tXARDS, after
CKE goes HIGH. Power-down exit latencies are defined in the AC spec table of this data sheet.
Asynchronous CKE LOW Event
DRAM requires CKE to be maintained “HIGH” for all valid operations as defined in this datasheet. If CKE
asynchronously drops “LOW” during any valid operation DRAM is not guaranteed to preserve the contents of
array. If this event occurs, memory controller must satisfy DRAM timing specification tDelay before turning off the
clocks. Stable clocks must exist at the input of DRAM before CKE is raised “HIGH” again. DRAM must be fully re-
initialized. DRAM is ready for normal operation after the initialization sequence.
Input clock frequency change during precharge power down
DDR2 SDRAM input clock frequency can be changed under following condition: DDR2 SDRAM is in precharged
power down mode. ODT must be turned off and CKE must be at logic LOW level. A minimum of 2 clocks must
be waited after CKE goes LOW before clock frequency may change. SDRAM input clock frequency is allowed to
change only within minimum and maximum operating frequency specified for the particular speed grade. During
input clock frequency change, ODT and CKE must be held at stable LOW levels. Once input clock frequency is
changed, stable new clocks must be provided to DRAM before precharge power down may be exited and DLL
must be RESET via EMRS after precharge power down exit. Depending on new clock frequency an additional
MRS command may need to be issued to appropriately set the WR, CL etc. During DLL re-lock period, ODT
must remain off. After the DLL lock time, the DRAM is ready to operate with new clock frequency.
No operation command
The No Operation Command should be used in cases when the DDR2 SDRAM is in an idle or a wait state. The
purpose of the No Operation Command (NOP) is to prevent the DDR2 SDRAM from registering any unwanted
commands between operations. A No Operation Command is registered when CS# is LOW with RAS#, CAS#,
and WE# held HIGH at the rising edge of the clock. A No Operation Command will not terminate a previous
operation that is still executing, such as a burst read or write cycle.
Deselect command
The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs
when CS# is brought HIGH at the rising edge of the clock, the RAS#, CAS#, and WE# signals become don’t
cares.
Confidential
19
Rev. 1.0
Feb. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
