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AS4C64M8D2-25BCN 参数 Datasheet PDF下载

AS4C64M8D2-25BCN图片预览
型号: AS4C64M8D2-25BCN
PDF下载: 下载PDF文件 查看货源
内容描述: [Fully synchronous operation]
分类和应用:
文件页数/大小: 59 页 / 1530 K
品牌: ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
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AS4C64M8D2  
Table 25. Electrical Characteristics and Recommended A.C. Operating Conditions  
(VDD = 1.8V 0.1V, TOPER = 0~95C)  
-25  
-3  
Specific  
Notes  
Symbol  
Parameter  
Unit  
Min.  
Max.  
Min.  
Max.  
CL=3  
5
8
8
5
3.75  
3
8
8
8
15, 33, 34  
15, 33, 34  
15, 33, 34  
15, 33, 34  
34, 35  
ns  
ns  
ns  
ns  
tCK  
tCK  
tCK  
CL=4  
CL=5  
CL=6  
3.75  
2.5  
Average clock period  
tCK(avg)  
8
2.5  
8
-
-
Average clock HIGH pulse width  
0.48  
0.48  
0.52  
0.52  
0.48  
0.48  
0.52  
tCH(avg)  
tCL(avg)  
WL  
Average Clock LOW pulse width  
0.52  
34, 35  
Write command to DQS associated clock edge  
RL-1  
RL-1  
DQS latching rising transitions to associated clock  
edges  
-0.25  
0.25  
-0.25  
0.25  
28  
28  
tDQSS  
tCK  
DQS falling edge to CK setup time  
DQS falling edge hold time from CK  
0.2  
0.2  
-
-
0.2  
0.2  
-
tDSS  
tDSH  
tCK  
tCK  
-
DQS input HIGH pulse width  
0.35  
-
0.35  
-
tDQSH  
tCK  
DQS input LOW pulse width  
Write preamble  
0.35  
0.35  
0.4  
-
-
0.35  
0.35  
0.4  
-
-
tDQSL  
tWPRE  
tWPST  
tCK  
tCK  
tCK  
Write postamble  
0.6  
0.6  
10  
5, 7, 9, 22,  
27  
Address and Control input setup time  
0.175  
-
0.2  
-
tIS(base)  
ns  
5, 7, 9, 23,  
27  
Address and Control input hold time  
Control & Address input pulse width for each input  
DQ & DM input setup time  
0.25  
0.6  
-
-
-
0.275  
0.6  
-
-
-
tIH(base)  
tIPW  
ns  
tCK  
ns  
6, 7, 8, 20,  
26, 29  
0.05  
0.1  
tDS(base)  
6, 7, 8, 21,  
26, 29  
DQ & DM input hold time  
0.125  
-
0.175  
-
tDH(base)  
ns  
DQ and DM input pulse width for each input  
DQ output access time from CK, CK#  
DQS output access time from CK, CK#  
Data-out high-impedance time from CK, CK#  
DQS(DQS#) low-impedance time from CK, CK#  
DQ low-impedance time from CK, CK#  
DQS-DQ skew for DQS and associated DQ signals  
CK half pulse width  
0.35  
-
0.35  
-0.45  
-0.4  
-
-
tDIPW  
tAC  
tDQSCK  
tHZ  
tLZ(DQS)  
tLZ(DQ)  
tDQSQ  
tCK  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCK  
tCK  
ns  
tCK  
ns  
ns  
ns  
ns  
tCK  
ns  
tCK  
tCK  
-0.4  
0.4  
0.35  
0.45  
0.4  
38  
38  
-0.35  
-
18, 38  
18, 38  
18, 38  
13  
tAC(max)  
tAC(max)  
tAC(min)  
tAC(max)  
tAC(min)  
tAC(max)  
2tAC(min)  
2tAC(min)  
tAC(max)  
0.2  
tAC(max)  
-
-
0.24  
min(tCL,tCH  
)
-
min(tCL,tCH  
)
11, 12, 35  
12, 36  
37  
tHP  
tQHS  
-
DQ hold skew factor  
-
tHP -tQHS  
0.9  
0.3  
-
0.34  
DQ/DQS output hold time from DQS  
Read preamble  
-
-
0.9  
tHP -tQHS  
tQH  
1.1  
1.1  
19, 39  
19, 40  
4, 30  
tRPRE  
tRPST  
tRRD  
tCCD  
tWR  
Read postamble  
0.4  
0.6  
0.4  
0.6  
Active to active command period  
CAS# to CAS# command delay  
10  
-
-
-
-
-
-
-
-
10  
-
-
-
-
-
2
2
Write recovery time  
15  
15  
30  
14, 31  
3, 24, 30  
3, 30  
25  
Auto Power write recovery + precharge time  
Internal Write to Read Command Delay  
Internal read to precharge command delay  
CKE minimum pulse width  
WR + tRP  
7.5  
WR + tRP  
7.5  
tDAL  
tWTR  
tRTP  
tCKE  
tXSNR  
tXSRD  
tXP  
7.5  
7.5  
3
tRFC+10  
200  
2
-
-
-
3
Exit self refresh to non-read command delay  
Exit self refresh to a read command  
Exit precharge power down to any command  
30  
t
RFC+10  
200  
2
-
-
-
-
Confidential  
24  
Rev. 1.0  
Feb. /2014  
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