AS4C16M16SA
Table 16. Electrical Characteristics and Recommended A.C. Operating Conditions
±
(VDD = 3.3V 0.3V, TA = -40~85°C) (Note: 5, 6, 7, 8)
-6
-7
Symbol
A.C. Parameter
Row cycle time
Unit Note
Min. Max. Min. Max.
tRC
60
60
18
-
-
-
63
63
21
-
-
-
(same bank)
tRFC
tRCD
Refresh cycle time
RAS# to CAS# delay
(same bank)
tRP
Precharge to refresh/row activate command
(same bank)
21
-
18
-
tRRD
Row activate to row activate delay
(different banks)
12
12
42
-
-
14
14
42
-
-
tMRD
tRAS
Mode register set cycle time
Row activate to precharge time
(same bank)
120K
120K
tWR
tCK
Write recovery time
12
10
6
-
-
14
10
7
-
ns
9
CL* = 2
-
Clock cycle time
CL* = 3
-
-
10
10
tCH
tCL
Clock high time
Clock low time
2
-
2.5
2.5
-
-
2
-
-
CL* = 2
-
6
5
-
6
Access time from CLK
10
9
tAC
(positive edge)
CL* = 3
-
-
5.4
tOH
tLZ
Data output hold time
Data output low impedance
Data output high impedance
2.5
0
2.5
0
-
-
-
tHZ
-
5
-
-
5.4
8
tIS
Data/Address/Control Input set-up time
Data/Address/Control Input hold time
Power Down Exit set-up time
1.5
0.8
1.5
0.8
-
-
10
10
tIH
-
tPDE
tREFI
tXSR
tIS+ CK
t
-
tIS+ CK
t
-
Average Refresh interval time
-
7.8
-
-
7.8
-
μs
Exit Self-Refresh to Read Command
tRC+ IS
t
tRC+ IS
t
ns
*
CL is CAS Latency.
Note:
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device.
2. All voltages are referenced to VSS. Overshoot VIH (Max) = 4.6V for pulse width ≤ 3ns. Undershoot VIL (Min) =
-1.0V for pulse width ≤ 3ns.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the
minimum value of tCK and tRC. Input signals are changed one time during every 2 tCK
.
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Power-up sequence is described in Note 11.
6. A.C. Test Conditions
Confidential
19
Rev. 2.0 63nm Mar /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
